DFT and BIST of a multichip module for high-energy physics experiments

Engineers at Politecnico di Torino designed a multichip module for high-energy physics experiments conducted on the Large Hadron Collider. An array of these MCMs handles multichannel data acquisition and signal processing. Testing the MCM from board to die level required a combination of DFT strategie

Techniques for Improving Security and Trustworthiness of Integrated Circuits

The integrated circuit (IC) development process is becoming increasingly vulnerable to malicious activities because untrusted parties could be involved in this IC development flow. There are four typical problems that impact the security and trustworthiness of ICs used in military, financial, transportation, or other critical systems: (i) Malicious inclusions and alterations, known as hardware Trojans, can be inserted into a design by modifying the design during GDSII development and fabrication. Hardware Trojans in ICs may cause malfunctions, lower the reliability of ICs, leak confidential information to adversaries or even destroy the system under specifically designed conditions. (ii) The number of circuit-related counterfeiting incidents reported by component manufacturers has increased significantly over the past few years with recycled ICs contributing the largest percentage of the total reported counterfeiting incidents. Since these recycled ICs have been used in the field before, the performance and reliability of such ICs has been degraded by aging effects and harsh recycling process. (iii) Reverse engineering (RE) is process of extracting a circuit’s gate-level netlist, and/or inferring its functionality. The RE causes threats to the design because attackers can steal and pirate a design (IP piracy), identify the device technology, or facilitate other hardware attacks. (iv) Traditional tools for uniquely identifying devices are vulnerable to non-invasive or invasive physical attacks. Securing the ID/key is of utmost importance since leakage of even a single device ID/key could be exploited by an adversary to hack other devices or produce pirated devices. In this work, we have developed a series of design and test methodologies to deal with these four challenging issues and thus enhance the security, trustworthiness and reliability of ICs. The techniques proposed in this thesis include: a path delay fingerprinting technique for detection of hardware Trojans, recycled ICs, and other types counterfeit ICs including remarked, overproduced, and cloned ICs with their unique identifiers; a Built-In Self-Authentication (BISA) technique to prevent hardware Trojan insertions by untrusted fabrication facilities; an efficient and secure split manufacturing via Obfuscated Built-In Self-Authentication (OBISA) technique to prevent reverse engineering by untrusted fabrication facilities; and a novel bit selection approach for obtaining the most reliable bits for SRAM-based physical unclonable function (PUF) across environmental conditions and silicon aging effects

Index to NASA Tech Briefs, January - June 1966

Index to NASA technological innovations for January-June 196

Innovative magnetorheological devices for shock and vibration mitigation

Vibration and impact protection have been a popular topic in research fields, which could directly affect the passengers’ and drivers’ comfort and safety, even cause spines fracture. Therefore, an increasing number of vehicle suspensions and aircraft landing gears are proposed and manufactured. Magnetorheological fluids (MRFs), as a smart material, are growly applied into the above device owing to its unique properties such as fast response, reversible properties, and broad controllable range, which could improve the vibration/impact mitigation performance. MRF was utilized to achieve adaptive parameters of the vehicle suspensions by controlling the magnetic field strength of the MRF working areas. Generally, the magnetic field is provided by a given current, subsequently, it would consume massive energy from a long-term perspective. Thus, a self-powered concept was applied as well. This thesis reports a compact stiffness controllable MR damper with a self-powered capacity. After the prototype of the MR damper, its property tests were conducted to verify the stiffness controllability and the energy generating ability using a hydraulic Instron test system. Then, a quarter-car test rig was built, and the semi-active MR suspension integrated with the self-powered MR damper was installed on a test rig. Two controllers, one based on short-time Fourier transform (STFT) and a classical skyhook controller was developed to control the stiffness. The evaluation results demonstrate that the proposed MR damper incorporated with STFT controller or skyhook controller could suppress the response displacements and accelerations obviously comparing with the conventional passive systems

A survey of scan-capture power reduction techniques

With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing