Evolutionary design of a full–envelope flight control system for an unstable fighter aircraft

The use of an evolutionary algorithm in the framework of H∞ control theory is being considered as a means for synthesizing controller gains that minimize a weighted combination of the infinite-norm of the sensitivity function (for disturbance attenuation requirements) and complementary sensitivity function (for robust stability requirements) at the same time. The case study deals with the stability and control augmentation of an unstable high-performance jet aircraft. Constraints on closed-loop response are also enforced, that represent typical requirements on airplane handling qualities, that makes the control law synthesis process more demanding. Gain scheduling is required, in order to obtain satisfactory performance over the whole flight envelope, so that the synthesis is performed at different reference trim conditions, for several values of the dynamic pressure, Q, used as the scheduling parameter. Nonetheless, the dynamic behaviour of the aircraft may exhibit significant variations when flying at different altitudes h, even for the same value of the dynamic pressure, so that a trade-off is required between different feasible controllers synthesized for a given value of Q, but different h. A multi-objective search is thus considered for the determination of the best suited solution to be introduced in the scheduling of the control law. The obtained results are then tested on a longitudinal nonlinear model of the aircraft

A Novel SAT-Based Approach to the Task Graph Cost-Optimal Scheduling Problem

The Task Graph Cost-Optimal Scheduling Problem consists in scheduling a certain number of interdependent tasks onto a set of heterogeneous processors (characterized by idle and running rates per time unit), minimizing the cost of the entire process. This paper provides a novel formulation for this scheduling puzzle, in which an optimal solution is computed through a sequence of Binate Covering Problems, hinged within a Bounded Model Checking paradigm. In this approach, each covering instance, providing a min-cost trace for a given schedule depth, can be solved with several strategies, resorting to Minimum-Cost Satisfiability solvers or Pseudo-Boolean Optimization tools. Unfortunately, all direct resolution methods show very low efficiency and scalability. As a consequence, we introduce a specialized method to solve the same sequence of problems, based on a traditional all-solution SAT solver. This approach follows the "circuit cofactoring" strategy, as it exploits a powerful technique to capture a large set of solutions for any new SAT counter-example. The overall method is completed with a branch-and-bound heuristic which evaluates lower and upper bounds of the schedule length, to reduce the state space that has to be visited. Our results show that the proposed strategy significantly improves the blind binate covering schema, and it outperforms general purpose state-of-the-art tool

A Multi-objective Perspective for Operator Scheduling using Fine-grained DVS Architecture

The stringent power budget of fine grained power managed digital integrated circuits have driven chip designers to optimize power at the cost of area and delay, which were the traditional cost criteria for circuit optimization. The emerging scenario motivates us to revisit the classical operator scheduling problem under the availability of DVFS enabled functional units that can trade-off cycles with power. We study the design space defined due to this trade-off and present a branch-and-bound(B/B) algorithm to explore this state space and report the pareto-optimal front with respect to area and power. The scheduling also aims at maximum resource sharing and is able to attain sufficient area and power gains for complex benchmarks when timing constraints are relaxed by sufficient amount. Experimental results show that the algorithm that operates without any user constraint(area/power) is able to solve the problem for most available benchmarks, and the use of power budget or area budget constraints leads to significant performance gain.Comment: 18 pages, 6 figures, International journal of VLSI design & Communication Systems (VLSICS

Evolutionary design of a full-envelope full-authority flight control system for an unstable high-performance aircraft

The use of an evolutionary algorithm in the framework of H1 control theory is being considered as a means for synthesizing controller gains that minimize a weighted combination of the infinite norm of the sensitivity function (for disturbance attenuation requirements) and complementary sensitivity function (for robust stability requirements) at the same time. The case study deals with a complete full-authority longitudinal control system for an unstable high-performance jet aircraft featuring (i) a stability and control augmentation system and (ii) autopilot functions (speed and altitude hold). Constraints on closed-loop response are enforced, that representing typical requirements on airplane handling qualities, that makes the control law synthesis process more demanding. Gain scheduling is required, in order to obtain satisfactory performance over the whole flight envelope, so that the synthesis is performed at different reference trim conditions, for several values of the dynamic pressure, used as the scheduling parameter. Nonetheless, the dynamic behaviour of the aircraft may exhibit significant variations when flying at different altitudes, even for the same value of the dynamic pressure, so that a trade-off is required between different feasible controllers synthesized at different altitudes for a given equivalent airspeed. A multiobjective search is thus considered for the determination of the best suited solution to be introduced in the scheduling of the control law. The obtained results are then tested on a longitudinal non-linear model of the aircraft

Using ACL2 to Verify Loop Pipelining in Behavioral Synthesis

Behavioral synthesis involves compiling an Electronic System-Level (ESL) design into its Register-Transfer Level (RTL) implementation. Loop pipelining is one of the most critical and complex transformations employed in behavioral synthesis. Certifying the loop pipelining algorithm is challenging because there is a huge semantic gap between the input sequential design and the output pipelined implementation making it infeasible to verify their equivalence with automated sequential equivalence checking techniques. We discuss our ongoing effort using ACL2 to certify loop pipelining transformation. The completion of the proof is work in progress. However, some of the insights developed so far may already be of value to the ACL2 community. In particular, we discuss the key invariant we formalized, which is very different from that used in most pipeline proofs. We discuss the needs for this invariant, its formalization in ACL2, and our envisioned proof using the invariant. We also discuss some trade-offs, challenges, and insights developed in course of the project.Comment: In Proceedings ACL2 2014, arXiv:1406.123

A survey of behavioral-level partitioning systems

Many approaches have been developed to partition a system's behavioral description before a structural implementation is synthesized. We highlight the foundations and motivations for behavioral partitioning. We survey behavioral partitioning approaches, discussing abstraction levels, goals, major steps, and key assumptions in each

Template Generation - A Graph Profiling Algorithm

The availability of high-level design entry tooling is crucial for the viability of any reconfigurable SoC architecture. This paper presents a template generation algorithm. The objective of template generation step is to extract functional equivalent structures, i.e. templates, from a control data flow graph. By profiling the graph, the algorithm generates all the possible templates and the corresponding matches. Using unique serial numbers and circle numbers, the algorithm can find all distinct templates with multiple outputs. A new type of graph (hydragraph) that can cope with multiple outputs is introduced. The generated templates pepresented by the hydragraph are not limited in shapes, i.e., we can find templates with multiple outputs or multiple sinks