1 research outputs found
Reliability-energy-performance optimisation in combinational circuits in presence of soft errors
PhD ThesisThe reliability metric has a direct relationship to the amount of value produced
by a circuit, similar to the performance metric. With advances in CMOS
technology, digital circuits become increasingly more susceptible to soft errors.
Therefore, it is imperative to be able to assess and improve the level of reliability
of these circuits. A framework for evaluating and improving the reliability of
combinational circuits is proposed, and an interplay between the metrics of
reliability, energy and performance is explored.
Reliability evaluation is divided into two levels of characterisation: stochastic
fault model (SFM) of the component library and a design-specific critical vector
model (CVM). The SFM captures the properties of components with regard to
the interference which causes error. The CVM is derived from a limited number
of simulation runs on the specific design at the design time and producing
the reliability metric. The idea is to move the high-complexity problem of the
stochastic characterisation of components to the generic part of the design
process, and to do it just once for a large number of specific designs. The
method is demonstrated on a range of circuits with various structures.
A three-way trade-off between reliability, energy, and performance has
been discovered; this trade-off facilitates optimisations of circuits and their
operating conditions.
A technique for improving the reliability of a circuit is proposed, based on
adding a slow stage at the primary output. Slow stages have the ability to
absorb narrow glitches from prior stages, thus reducing the error probability.
Such stages, or filters, suppress most of the glitches generated in prior stages
and prevent them from arriving at the primary output of the circuit. Two filter
solutions have been developed and analysed. The results show a dramatic
improvement in reliability at the expense of minor performance and energy
penalties.
To alleviate the problem of the time-consuming analogue simulations involved in the proposed method, a simplification technique is proposed. This
technique exploits the equivalence between the properties of the gates within
a path and the equivalence between paths. On the basis of these equivalences,
it is possible to reduce the number of simulation runs. The effectiveness of
the proposed technique is evaluated by applying it to different circuits with
a representative variety of path topologies. The results show a significant
decrease in the time taken to estimate reliability at the expense of a minor
decrease in the accuracy of estimation. The simplification technique enables
the use of the proposed method in applications with complex circuits.Ministry of Education and Scientific Research in Liby