Fuzzy logic-based embedded system for video de-interlacing

Video de-interlacing algorithms perform a crucial task in video processing. Despite these algorithms are developed using software implementations, their implementations in hardware are required to achieve real-time operation. This paper describes the development of an embedded system for video de-interlacing. The algorithm for video de-interlacing uses three fuzzy logic-based systems to tackle three relevant features in video sequences: motion, edges, and picture repetition. The proposed strategy implements the algorithm as a hardware IP core on a FPGA-based embedded system. The paper details the proposed architecture and the design methodology to develop it. The resulting embedded system is verified on a FPGA development board and it is able to de-interlace in real-tim

Edge-adaptive spatial video de-interlacing algorithms based on fuzzy logic

Since the human visual system is especially sensitive to image edges, edge-dependent spatial interpolators have been proposed in literature as a means of successfully restoring edges while avoiding the staircase effect of linear spatial algorithms. This paper addresses the application of video de-interlacing, which constitutes an indispensable stage in video format conversion. Classic edge-adaptive de-interlacing algorithms introduce annoying artifacts when the edge directions are evaluated incorrectly. This paper presents two ways of exploiting fuzzy reasoning to reinforce edges without an excessive increase in computational complexity. The performance of the proposed algorithms is analyzed by de-interlacing a wide set of test sequences. The study compares the two proposals both with each other and with other edge-adaptive de-interlacing methods reported in the recent literatur

Fuzzy logic-based embedded system for video de-interlacing

Video de-interlacing algorithms perform a crucial task in video processing. Despite these algorithms are developed using software implementations, their implementations in hardware are required to achieve real-time operation. This paper describes the development of an embedded system for video de-interlacing. The algorithm for video de-interlacing uses three fuzzy logic-based systems to tackle three relevant features in video sequences: motion, edges, and picture repetition. The proposed strategy implements the algorithm as a hardware IP core on a FPGA-based embedded system. The paper details the proposed architecture and the design methodology to develop it. The resulting embedded system is verified on a FPGA development board and it is able to de-interlace in real-time. © 2013 Elsevier B.V. All rights reserved.This work was partially supported by MOBY-DIC project FP7-INFSO-ICT-248858 (www.mobydic-project.eu) from EuropeanCommunity, TEC2011-24319 project from the Spanish Govern-ment, and P08-TIC-03674 project from the Andalusian Regional Government (with support from the PO FEDER). P. Brox is supportedunder the post-doctoral program called ‘Juan de la Cierva’ from theSpanish Ministry of Science and Innovation.Peer Reviewe