A 24-GHz CMOS Front-End

This paper reports the first 24-GHz CMOS front-end in a 0.18-µm process. It consists of a low-noise amplifier (LNA) and a mixer and downconverts an RF input at 24GHz to an IF of 5 GHz. It has a power gain of 27.5 dB and an overall noise figure of 7.7 dB with an input return loss, S[sub]11 of 21 dB consuming 20 mA from a 1.5-V supply. The LNA achieves a power gain of 15 dB and a noise figure of 6 dB on 16 mA of dc current. The LNA’s input stage utilizes a common-gate with resistive feedthrough topology. The performance analysis of this topology predicts the experimental results with good accuracy

High Dynamic Range RF Front End with Noise Cancellation and Linearization for WiMAX Receivers

This research deals with verification of the high dynamic range for a heterodyne radio frequency (RF) front end. A 2.6 GHz RF front end is designed and implemented in a hybrid microwave integrated circuit (HMIC) for worldwide interoperability for microwave access (WiMAX) receivers. The heterodyne RF front end consists of a low-noise amplifier (LNA) with noise cancellation, an RF bandpass filter (BPF), a downconverter with linearization, and an intermediate frequency (IF) BPF. A noise canceling technique used in the low-noise amplifier eliminates a thermal noise and then reduces the noise figure (NF) of the RF front end by 0.9 dB. Use of a downconverter with diode linearizer also compensates for gain compression, which increases the input-referred third-order intercept point (IIP3) of the RF front end by 4.3 dB. The proposed method substantially increases the spurious-free dynamic range (DRf) of the RF front end by 3.5 dB

The BTeV RICH Front End Electronics

We report on the design and testing of novel mixed analog and digital front end ASICs custom made for the single photon detectors considered for the BTeV RICH system. The key features are reviewed, as well as results achieved using electronics bench tests and beam studies.Comment: 7 pages, 4 figures, talk given at the 5th International Workshop on Ring Imaging Cherenkov Counters (RICH2004

A Subband-Based SVM Front-End for Robust ASR

This work proposes a novel support vector machine (SVM) based robust automatic speech recognition (ASR) front-end that operates on an ensemble of the subband components of high-dimensional acoustic waveforms. The key issues of selecting the appropriate SVM kernels for classification in frequency subbands and the combination of individual subband classifiers using ensemble methods are addressed. The proposed front-end is compared with state-of-the-art ASR front-ends in terms of robustness to additive noise and linear filtering. Experiments performed on the TIMIT phoneme classification task demonstrate the benefits of the proposed subband based SVM front-end: it outperforms the standard cepstral front-end in the presence of noise and linear filtering for signal-to-noise ratio (SNR) below 12-dB. A combination of the proposed front-end with a conventional front-end such as MFCC yields further improvements over the individual front ends across the full range of noise levels

A High TCMRR, Inherently Charge Balanced Bidirectional Front-End for Multichannel Closed-Loop Neuromodulation

This paper describes a multichannel bidirectional front-end for implantable closed-loop neuromodulation. Stimulation artefacts are reduced by way of a 4-channel H-bridge current source sharing stimulator front-end that minimizes residual charge drops in the electrodes via topology-inherent charge balancing. A 4-channel chopper front-end is capable of multichannel recording in the presence of artefacts as a result of its high total common-mode rejection ratio (TCMRR) that accounts for CMRR degradation due to electrode mismatch. Experimental verification of a prototype fabricated in a standard 180 nm process shows a stimulator front-end with 0.059% charge balance and 0.275 nA DC current error. The recording front-end consumes 3.24 µW, tolerates common-mode interference up to 1 Vpp and shows a TCMRR > 66 dB for 500 mVpp inputs.Ministerio de Economía y Competitividad TEC2016-80923-POffice of Naval Research (USA) N00014111031

Phobos: A front-end approach to extensible compilers (long version)

This paper describes a practical approach for implementing certain types of domain-specific languages with extensible compilers. Given a compiler with one or more front-end languages, we introduce the idea of a "generic" front-end that allows the syntactic and semantic specification of domain-specific languages. Phobos, our generic front-end, offers modular language specification, allowing the programmer to define new syntax and semantics incrementally

Front-End electronics configuration system for CMS

The four LHC experiments at CERN have decided to use a commercial SCADA (Supervisory Control And Data Acquisition) product for the supervision of their DCS (Detector Control System). The selected SCADA, which is therefore used for the CMS DCS, is PVSS II from the company ETM. This SCADA has its own database, which is suitable for storing conventional controls data such as voltages, temperatures and pressures. In addition, calibration data and FE (Front-End) electronics configuration need to be stored. The amount of these data is too large to be stored in the SCADA database [1]. Therefore an external database will be used for managing such data. However, this database should be completely integrated into the SCADA framework, it should be accessible from the SCADA and the SCADA features, e.g. alarming, logging should be benefited from. For prototyping, Oracle 8i was selected as the external database manager. The development of the control system for calibration constants and FE electronics configuration has been done in close collaboration with the CMS tracker group and JCOP (Joint COntrols Project)(1). (1)The four LHC experiments and the CERN IT/CO group has merged their efforts to build the experiments controls systems and set up the JCOP at the end of December, 1997 for this purpose.Comment: 3 pages, 4 figures, Icaleps'01 conference PSN WEDT00

The CMS Tracker Readout Front End Driver

The Front End Driver, FED, is a 9U 400mm VME64x card designed for reading out the Compact Muon Solenoid, CMS, silicon tracker signals transmitted by the APV25 analogue pipeline Application Specific Integrated Circuits. The FED receives the signals via 96 optical fibers at a total input rate of 3.4 GB/sec. The signals are digitized and processed by applying algorithms for pedestal and common mode noise subtraction. Algorithms that search for clusters of hits are used to further reduce the input rate. Only the cluster data along with trigger information of the event are transmitted to the CMS data acquisition system using the S-LINK64 protocol at a maximum rate of 400 MB/sec. All data processing algorithms on the FED are executed in large on-board Field Programmable Gate Arrays. Results on the design, performance, testing and quality control of the FED are presented and discussed