Short Distance Telemetry for Piston Monitoring. Design and Development of Short Distance Telemetry for Engine Condition Monitoring.

Piston telemetry research involves monitoring the temperatures at specific internal location points within a combustion engine piston. The temperatures are detected with type K thermocouples as voltages and processed to convert them into temperatures using cold junction compensation methods. The present system uses a specific sensor designed to operate in the high temperature environment within the piston, reading multiple thermocouples. Because of the reciprocating motion of the piston, power generation is intermittent and available only when the piston reaches near bottom dead centre, using inductive coupling to power the sensors and transmit data to an evaluation unit for data processing. The planned system involves designing and building a prototype telemetry unit using ¿off the shelf¿ components that integrate the reading of thermocouple outputs, signal processing and cold junction compensation. Wireless telemetry is adopted for data transmission with an integrated Bluetooth and microcontroller module. The data acquisition module can be adapted for other sensors by adapting the firmware uploaded to the microcontroller. The hardware electronics are envisaged to be encased in thermal insulation to enable operation in high temperature environments. The considered system requires a power supply for the integrated components in the form of a power generator and that it should meet two criteria: to be located within confined spaces and to be permanently available, without having to dismantle systems to change batteries. The selected method is an induction generator constructed from a coil stator connected to the piston connection rod big end and a permanent magnet rotor connected to the crankshaft. The suggested mechatronic system is validated against the present system by comparing both systems to determine whether wireless telemetry can perform within acceptable tolerances and limits for the specified task. Then, for acceptable performances, reduce costs and include flexibility to operate in multiple environments. Bench testing shows that the power generator is capable of driving the sensors and the Bluetooth integrated DAQ system.EPSRC and University of Bradfor

Formal Verification and In-Situ Test of Analog and Mixed-Signal Circuits

As CMOS technologies continuously scale down, designing robust analog and mixed-signal (AMS) circuits becomes increasingly difficult. Consequently, there are pressing needs for AMS design checking techniques, more specifically design verification and design for testability (DfT). The purpose of verification is to ensure that the performance of an AMS design meets its specification under process, voltage and temperature (PVT) variations and different working conditions, while DfT techniques aim at embedding testability into the design, by adding auxiliary circuitries for testing purpose. This dissertation focuses on improving the robustness of AMS designs in highly scaled technologies, by developing novel formal verification and in-situ test techniques. Compared with conventional AMS verification that relies more on heuristically chosen simulations, formal verification provides a mathematically rigorous way of checking the target design property. A formal verification framework is proposed that incorporates nonlinear SMT solving techniques and simulation exploration to efficiently verify the dynamic properties of AMS designs. A powerful Bayesian inference based technique is applied to dynamically tradeoff between the costs of simulation and nonlinear SMT. The feasibility and efficacy of the proposed methodology are demonstrated on the verification of lock time specification of a charge-pump PLL. The powerful and low-cost digital processing capabilities of today?s CMOS technologies are enabling many new in-situ test schemes in a mixed-signal environment. First, a novel two-level structure of GRO-PVDL is proposed for on-chip jitter testing of high-speed high-resolution applications with a gated ring oscillator (GRO) at the first level to provide a coarse measurement and a Vernier-style structure at the second level to further measure the residue from the first level with a fine resolution. With the feature of quantization noise shaping, an effective resolution of 0.8ps can be achieved using a 90nm CMOS technology. Second, the reconfigurability of recent all-digital PLL designs is exploited to provide in-situ output jitter test and diagnosis abilities under multiple parametric variations of key analog building blocks. As an extension, an in-situ test scheme is proposed to provide online testing for all-digital PLL based polar transmitters