Sound and Automated Synthesis of Digital Stabilizing Controllers for Continuous Plants

Modern control is implemented with digital microcontrollers, embedded within a dynamical plant that represents physical components. We present a new algorithm based on counter-example guided inductive synthesis that automates the design of digital controllers that are correct by construction. The synthesis result is sound with respect to the complete range of approximations, including time discretization, quantization effects, and finite-precision arithmetic and its rounding errors. We have implemented our new algorithm in a tool called DSSynth, and are able to automatically generate stable controllers for a set of intricate plant models taken from the literature within minutes.Comment: 10 page

고속 시리얼 링크를 위한 고리 발진기를 기반으로 하는 주파수 합성기

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 정덕균.In this dissertation, major concerns in the clocking of modern serial links are discussed. As sub-rate, multi-standard architectures are becoming predominant, the conventional clocking methodology seems to necessitate innovation in terms of low-cost implementation. Frequency synthesis with active, inductor-less oscillators replacing LC counterparts are reviewed, and solutions for two major drawbacks are proposed. Each solution is verified by prototype chip design, giving a possibility that the inductor-less oscillator may become a proper candidate for future high-speed serial links. To mitigate the high flicker noise of a high-frequency ring oscillator (RO), a reference multiplication technique that effectively extends the bandwidth of the following all-digital phase-locked loop (ADPLL) is proposed. The technique avoids any jitter accumulation, generating a clean mid-frequency clock, overall achieving high jitter performance in conjunction with the ADPLL. Timing constraint for the proper reference multiplication is first analyzed to determine the calibration points that may correct the existent phase errors. The weight for each calibration point is updated by the proposed a priori probability-based least-mean-square (LMS) algorithm. To minimize the time required for the calibration, each gain for the weight update is adaptively varied by deducing a posteriori which error source dominates the others. The prototype chip is fabricated in a 40-nm CMOS technology, and its measurement results verify the low-jitter, high-frequency clock generation with fast calibration settling. The presented work achieves an rms jitter of 177/223 fs at 8/16-GHz output, consuming 12.1/17-mW power. As the second embodiment, an RO-based ADPLL with an analog technique that addresses the high supply sensitivity of the RO is presented. Unlike prior arts, the circuit for the proposed technique does not extort the RO voltage headroom, allowing high-frequency oscillation. Further, the performance given from the technique is robust over process, voltage, and temperature (PVT) variations, avoiding the use of additional calibration hardware. Lastly, a comprehensive analysis of phase noise contribution is conducted for the overall ADPLL, followed by circuit optimizations, to retain the low-jitter output. Implemented in a 40-nm CMOS technology, the frequency synthesizer achieves an rms jitter of 289 fs at 8 GHz output without any injected supply noise. Under a 20-mVrms white supply noise, the ADPLL suppresses supply-noise-induced jitter by -23.8 dB.본 논문은 현대 시리얼 링크의 클락킹에 관여되는 주요한 문제들에 대하여 기술한다. 준속도, 다중 표준 구조들이 채택되고 있는 추세에 따라, 기존의 클라킹 방법은 낮은 비용의 구현의 관점에서 새로운 혁신을 필요로 한다. LC 공진기를 대신하여 능동 소자 발진기를 사용한 주파수 합성에 대하여 알아보고, 이에 발생하는 두가지 주요 문제점과 각각에 대한 해결 방안을 탐색한다. 각 제안 방법을 프로토타입 칩을 통해 그 효용성을 검증하고, 이어서 능동 소자 발진기가 미래의 고속 시리얼 링크의 클락킹에 사용될 가능성에 대해 검토한다. 첫번째 시연으로써, 고주파 고리 발진기의 높은 플리커 잡음을 완화시키기 위해 기준 신호를 배수화하여 뒷단의 위상 고정 루프의 대역폭을 효과적으로 극대화 시키는 회로 기술을 제안한다. 본 기술은 지터를 누적 시키지 않으며 따라서 깨끗한 중간 주파수 클락을 생성시켜 위상 고정 루프와 함께 높은 성능의 고주파 클락을 합성한다. 기준 신호를 성공적으로 배수화하기 위한 타이밍 조건들을 먼저 분석하여 타이밍 오류를 제거하기 위한 방법론을 파악한다. 각 교정 중량은 연역적 확률을 기반으로한 LMS 알고리즘을 통해 갱신되도록 설계된다. 교정에 필요한 시간을 최소화 하기 위하여, 각 교정 이득은 타이밍 오류 근원들의 크기를 귀납적으로 추론한 값을 바탕으로 지속적으로 제어된다. 40-nm CMOS 공정으로 구현된 프로토타입 칩의 측정을 통해 저소음, 고주파 클락을 빠른 교정 시간안에 합성해 냄을 확인하였다. 이는 177/223 fs의 rms 지터를 가지는 8/16 GHz의 클락을 출력한다. 두번째 시연으로써, 고리 발진기의 높은 전원 노이즈 의존성을 완화시키는 기술이 포함된 주파수 합성기가 설계되었다. 이는 고리 발진기의 전압 헤드룸을 보존함으로서 고주파 발진을 가능하게 한다. 나아가, 전원 노이즈 감소 성능은 공정, 전압, 온도 변동에 대하여 민감하지 않으며, 따라서 추가적인 교정 회로를 필요로 하지 않는다. 마지막으로, 위상 노이즈에 대한 포괄적 분석과 회로 최적화를 통하여 주파수 합성기의 저잡음 출력을 방해하지 않는 방법을 고안하였다. 해당 프로토타입 칩은 40-nm CMOS 공정으로 구현되었으며, 전원 노이즈가 인가되지 않은 상태에서 289 fs의 rms 지터를 가지는 8 GHz의 클락을 출력한다. 또한, 20 mVrms의 전원 노이즈가 인가되었을 때에 유도되는 지터의 양을 -23.8 dB 만큼 줄이는 것을 확인하였다.1 Introduction 1 1.1 Motivation 3 1.1.1 Clocking in High-Speed Serial Links 4 1.1.2 Multi-Phase, High-Frequency Clock Conversion 8 1.2 Dissertation Objectives 10 2 RO-Based High-Frequency Synthesis 12 2.1 Phase-Locked Loop Fundamentals 12 2.2 Toward All-Digital Regime 15 2.3 RO Design Challenges 21 2.3.1 Oscillator Phase Noise 21 2.3.2 Challenge 1: High Flicker Noise 23 2.3.3 Challenge 2: High Supply Noise Sensitivity 26 3 Filtering RO Noise 28 3.1 Introduction 28 3.2 Proposed Reference Octupler 34 3.2.1 Delay Constraint 34 3.2.2 Phase Error Calibration 38 3.2.3 Circuit Implementation 51 3.3 IL-ADPLL Implementation 55 3.4 Measurement Results 59 3.5 Summary 63 4 RO Supply Noise Compensation 69 4.1 Introduction 69 4.2 Proposed Analog Closed Loop for Supply Noise Compensation 72 4.2.1 Circuit Implementation 73 4.2.2 Frequency-Domain Analysis 76 4.2.3 Circuit Optimization 81 4.3 ADPLL Implementation 87 4.4 Measurement Results 90 4.5 Summary 98 5 Conclusions 99 A Notes on the 8REF 102 B Notes on the ACSC 105박

RF MEMS reference oscillators platform for wireless communications

A complete platform for RF MEMS reference oscillator is built to replace bulky quartz from mobile devices, thus reducing size and cost. The design targets LTE transceivers. A low phase noise 76.8 MHz reference oscillator is designed using material temperature compensated AlN-on-silicon resonator. The thesis proposes a system combining piezoelectric resonator with low loading CMOS cross coupled series resonance oscillator to reach state-of-the-art LTE phase noise specifications. The designed resonator is a two port fundamental width extensional mode resonator. The resonator characterized by high unloaded quality factor in vacuum is designed with low temperature coefficient of frequency (TCF) using as compensation material which enhances the TCF from - 3000 ppm to 105 ppm across temperature ranges of -40˚C to 85˚C. By using a series resonant CMOS oscillator, phase noise of -123 dBc/Hz at 1 kHz, and -162 dBc/Hz at 1MHz offset is achieved. The oscillator’s integrated RMS jitter is 106 fs (10 kHz–20 MHz), consuming 850 μA, with startup time is 250μs, achieving a Figure-of-merit (FOM) of 216 dB. Electronic frequency compensation is presented to further enhance the frequency stability of the oscillator. Initial frequency offset of 8000 ppm and temperature drift errors are combined and further addressed electronically. A simple digital compensation circuitry generates a compensation word as an input to 21 bit MASH 1 -1-1 sigma delta modulator incorporated in RF LTE fractional N-PLL for frequency compensation. Temperature is sensed using low power BJT band-gap front end circuitry with 12 bit temperature to digital converter characterized by a resolution of 0.075˚C. The smart temperature sensor consumes only 4.6 μA. 700 MHz band LTE signal proved to have the stringent phase noise and frequency resolution specifications among all LTE bands. For this band, the achieved jitter value is 1.29 ps and the output frequency stability is 0.5 ppm over temperature ranges from -40˚C to 85˚C. The system is built on 32nm CMOS technology using 1.8V IO device

Automatic calibration of modulated fractional-N frequency synthesizers

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.Includes bibliographical references (p. 145-148).This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.The focus of this research has been the development of a low power, radio frequency transmitter architecture. Specifically, a technique for in service automatic calibration of a modulated phase locked loop (PLL) frequency synthesizer has been developed. Phase/frequency modulation is accomplished by modulating the feedback divide value in a phase locked loop frequency synthesizer. A digital precompensation filter is used to extend the modulation bandwidth by canceling the low-pass transfer function of the PLL. The automatic calibration circuit maintains accurate matching between the digital precompensation filter and the analog PLL transfer function across process and temperature variations. The automatic calibration circuit, which is the main contribution of this thesis, operates while the transmitter is in service. This online calibration eliminates the need for production calibration and periodic down time for calibration cycles.(cont.) In addition the calibration circuitry provides greater accuracy in the modulation than what is possible via offline methods of calibration. The calibration circuit works with M-ary GFSK as well as 2 level GFSK. The automatic calibration circuit has been implemented in two forms to prove its operation. The first version is a circuit board level implementation with a center frequency of around 60 MHz. The second implementation of the system is in a full custom 0.6 ,Lm BiCMOS integrated circuit. The integrated circuit contains the complete synthesizer with automatic calibration and operates in the 1.88 GHz frequency band used by the Digital European Cordless Telephone (DECT) standard. A data rate of 2.5 Mbps using 2 level GFSK and 5.0 Mbps using 4 level GFSK has been achieved with a power consumption of 78 mW.by Daniel R. McMahill.Ph.D

Applications of the optical fiber to the generation and to the measurement of low-phase-noise microwave signals

The optical fiber used as a microwave delay line exhibits high stability and low noise and makes accessible a long delay (>100 microseconds) in a wide bandwidth (about 40 GHz, limited by the optronic components). Hence, it finds applications as the frequency reference in microwave oscillators and as the reference discriminator for the measurement of phase noise. The fiber is suitable to measure the oscillator stability with a sensitivity of parts in 1E-12. Enhanced sensitivity is obtained with two independent delay lines, after correlating and averaging. Short-term stability of parts in 1E-12 is achieved inserting the delay line in an oscillator. The frequency can be set in steps multiple of the inverse delay, which is in the 10-100 kHz region. This article adds to the available references a considerable amount of engineering and practical knowledge, the understanding of 1/f noise, calibration, the analysis of the cross-spectrum technique to reduce the instrument background, the phase-noise model of the oscillator, and the experimental test of the oscillator model.Comment: 23 pages, 13 figures, 41 reference

Transceiver architectures and sub-mW fast frequency-hopping synthesizers for ultra-low power WSNs

Wireless sensor networks (WSN) have the potential to become the third wireless revolution after wireless voice networks in the 80s and wireless data networks in the late 90s. This revolution will finally connect together the physical world of the human and the virtual world of the electronic devices. Though in the recent years large progress in power consumption reduction has been made in the wireless arena in order to increase the battery life, this is still not enough to achieve a wide adoption of this technology. Indeed, while nowadays consumers are used to charge batteries in laptops, mobile phones and other high-tech products, this operation becomes infeasible when scaled up to large industrial, enterprise or home networks composed of thousands of wireless nodes. Wireless sensor networks come as a new way to connect electronic equipments reducing, in this way, the costs associated with the installation and maintenance of large wired networks. To accomplish this task, it is necessary to reduce the energy consumption of the wireless node to a point where energy harvesting becomes feasible and the node energy autonomy exceeds the life time of the wireless node itself. This thesis focuses on the radio design, which is the backbone of any wireless node. A common approach to radio design for WSNs is to start from a very simple radio (like an RFID) adding more functionalities up to the point in which the power budget is reached. In this way, the robustness of the wireless link is traded off for power reducing the range of applications that can draw benefit form a WSN. In this thesis, we propose a novel approach to the radio design for WSNs. We started from a proven architecture like Bluetooth, and progressively we removed all the functionalities that are not required for WSNs. The robustness of the wireless link is guaranteed by using a fast frequency hopping spread spectrum technique while the power budget is achieved by optimizing the radio architecture and the frequency hopping synthesizer Two different radio architectures and a novel fast frequency hopping synthesizer are proposed that cover the large space of applications for WSNs. The two architectures make use of the peculiarities of each scenario and, together with a novel fast frequency hopping synthesizer, proved that spread spectrum techniques can be used also in severely power constrained scenarios like WSNs. This solution opens a new window toward a radio design, which ultimately trades off flexibility, rather than robustness, for power consumption. In this way, we broadened the range of applications for WSNs to areas in which security and reliability of the communication link are mandatory

Hybrid DDS-PLL based reconfigurable oscillators with high spectral purity for cognitive radio

Analytical, design and simulation studies on the performance optimization of reconfigurable architecture of a Hybrid DDS – PLL are presented in this thesis. The original contributions of this thesis are aimed towards the DDS, the dithering (spur suppression) scheme and the PLL. A new design of Taylor series-based DDS that reduces the dynamic power and number of multipliers is a significant contribution of this thesis. This thesis compares dynamic power and SFDR achieved in the design of varieties of DDS such as Quartic, Cubic, Linear and LHSC. This thesis proposes two novel schemes namely “Hartley Image Suppression” and “Adaptive Sinusoidal Interference Cancellation” overcoming the low noise floor of traditional dithering schemes. The simulation studies on a Taylor series-based DDS reveal an improvement in SFDR from 74 dB to 114 dB by using Least Mean Squares -Sinusoidal Interference Canceller (LM-SIC) with the noise floor maintained at -200 dB. Analytical formulations have been developed for a second order PLL to relate the phase noise to settling time and Phase Margin (PM) as well as to relate jitter variance and PM. New expressions relating phase noise to PM and lock time to PM are derived. This thesis derives the analytical relationship between the roots of the characteristic equation of a third order PLL and its performance metrics like PM, Gardner’s stability factor, jitter variance, spur gain and ratio of noise power to carrier power. This thesis presents an analysis to relate spur gain and capacitance ratio of a third order PLL. This thesis presents an analytical relationship between the lock time and the roots of its characteristic equation of a third order PLL. Through Vieta’s circle and Vieta’s angle, the performance metrics of a third order PLL are related to the real roots of its characteristic equation

A modified low roundoff digital oscillator design

The work of this thesis is to summarize and compares the existing digital oscillator design methods and combine them to form a modified structure for oscillator design. First of all, a combined structure of complex oscillator design is proposed. The structure combines the advantages of low hardware complexity and low roundoff errors. Then based on the suggested complex oscillator structure, some new digital oscillator structures with uniform frequency spacing are suggested. The new structures are also the modified structure of the existing oscillator. By adding power-of-two shift boxes into the modified structure, dynamic range of the output is enlarged and the quantization errors are greatly reduced. The modified oscillators can generate low frequency and low amplitude sinusoid waves with very small phase and amplitude deviation. In order to further reduce the quantization errors, error feedback circuits is applied into the circuit to further reduce the errors