958 research outputs found
Formal verification of pipelined microprocessors
Subject of this thesis is the formal verification of pipelined microprocessors.
This includes processors with state of the art schedulers, such as
the Tomasulo scheduler and speculation. In contrast to most of the literature,
we verify synthesizable design at gate level. Furthermore, we prove
both data consistency and liveness. We verify the proofs using the theorem
proving system PVS. We verify both in-order and out-of-order machines.
For verifying in-order machines, we extend the stall engine concept presented
in [MP00]. We describe and implement an algorithm that does the
transformation into a pipelined machine. We describe a generic machine
that supports speculating on arbitraty values. We formally verify proofs
for the Tomasulo scheduling algorithm with reorder buffer.Gegenstand dieser Dissertation ist die formale Verifikation von Mikroprozessoren
mit Pipeline. Dies beinhaltet auch Prozessoren mit aktuellen
Scheduling-Verfahren wie den Tomasulo Scheduler und spekulativer Ausfuehrung.
Im Gegensatz zu weiten Teilen der bestehenden Literatur fuehren
wir die Verifikation auf Gatter-Ebene durch. Des weitern beweisen wir
sowohl Datenkonsistenz als auch eine obere Schranke fuer die Ausfuehrungszeit.
Die Beweise werden mit dem Theorem Beweissystem PVS
verifiziert. Es werden sowohl in-order Maschinen als auch out-of-order
Maschinen verifiziert. Zur Verifikation der in-order Maschinen erweitern
wir die Stall Engine aus [MP00]. Wir beschreiben und Implementieren ein
Verfahren das die Transformation in die "pipelined machine\u27; durchfuehrt.
Wir beschreiben eine generische Maschine die Spekulation auf beliebige
Werte erlaubt. Wir verifizieren die Beweise fuer den Tomasulo Scheduler
mit Reorder Buffer
Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic
The logic of equality with uninterpreted functions (EUF) provides a means of
abstracting the manipulation of data by a processor when verifying the
correctness of its control logic. By reducing formulas in this logic to
propositional formulas, we can apply Boolean methods such as Ordered Binary
Decision Diagrams (BDDs) and Boolean satisfiability checkers to perform the
verification.
We can exploit characteristics of the formulas describing the verification
conditions to greatly simplify the propositional formulas generated. In
particular, we exploit the property that many equations appear only in positive
form. We can therefore reduce the set of interpretations of the function
symbols that must be considered to prove that a formula is universally valid to
those that are ``maximally diverse.''
We present experimental results demonstrating the efficiency of this approach
when verifying pipelined processors using the method proposed by Burch and
Dill.Comment: 46 page
Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation
Detailed modeling of processors and high performance cycle-accurate
simulators are essential for today's hardware and software design. These
problems are challenging enough by themselves and have seen many previous
research efforts. Addressing both simultaneously is even more challenging, with
many existing approaches focusing on one over another. In this paper, we
propose the Reduced Colored Petri Net (RCPN) model that has two advantages:
first, it offers a very simple and intuitive way of modeling pipelined
processors; second, it can generate high performance cycle-accurate simulators.
RCPN benefits from all the useful features of Colored Petri Nets without
suffering from their exponential growth in complexity. RCPN processor models
are very intuitive since they are a mirror image of the processor pipeline
block diagram. Furthermore, in our experiments on the generated cycle-accurate
simulators for XScale and StrongArm processor models, we achieved an order of
magnitude (~15 times) speedup over the popular SimpleScalar ARM simulator.Comment: Submitted on behalf of EDAA (http://www.edaa.com/
A Systematic Methodology for Verifying Superscalar Microprocessors
We present a systematic approach to decompose and incrementally build the proof of correctness of pipelined microprocessors. The central idea is to construct the abstraction function by using completion functions, one per unfinished instruction, each of which specifies the effect (on the observables) of completing the instruction. In addition to avoiding the term size and case explosion problem that limits the pure flushing approach, our method helps localize errors, and also handles stages with interactive loops. The technique is illustrated on pipelined and superscalar pipelined implementations of a subset of the DLX architecture. It has also been applied to a processor with out-of-order execution
Using ACL2 to Verify Loop Pipelining in Behavioral Synthesis
Behavioral synthesis involves compiling an Electronic System-Level (ESL)
design into its Register-Transfer Level (RTL) implementation. Loop pipelining
is one of the most critical and complex transformations employed in behavioral
synthesis. Certifying the loop pipelining algorithm is challenging because
there is a huge semantic gap between the input sequential design and the output
pipelined implementation making it infeasible to verify their equivalence with
automated sequential equivalence checking techniques. We discuss our ongoing
effort using ACL2 to certify loop pipelining transformation. The completion of
the proof is work in progress. However, some of the insights developed so far
may already be of value to the ACL2 community. In particular, we discuss the
key invariant we formalized, which is very different from that used in most
pipeline proofs. We discuss the needs for this invariant, its formalization in
ACL2, and our envisioned proof using the invariant. We also discuss some
trade-offs, challenges, and insights developed in course of the project.Comment: In Proceedings ACL2 2014, arXiv:1406.123
Decomposing the proof of correctness of pipelined microprocessors
technical reportWe present a systematic approach to decompose and incrementally build the proof of correctness of pipelined microprocessors. The central idea is to construct the abstraction function using completion functions, one per unfinished instruction, each of which specify the effect (on the observables) of completing the instruction. In addition to avoiding term-size and case explosion as could happen for deep and complex pipelines during flushing and helping localize errors, our method can also handle stages with iterative loops. The technique is illustrated on pipelined- as well as a superscalar pipelined implementations of a subset of the DLX architecture
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