Specifying Hardware Timing with ET-LOTOS (extended version)

It is explained how DILL (Digital Logic in LOTOS) can be used to specify and analyse hardware timing characteristics using ET-LOTOS (Enhanced Timed LOTOS), a timed extension of the ISO standard formal language LOTOS (Language of Temporal Ordering Specification). Hardware component functionality and timing characteristics are rigorously specified and then validated. As will be seen, subtle timing problems can be found by using this approach

Formally-Based Design Evaluation (extended version)

This paper investigates specification, verification and test generation for synchronous and asynchronous circuits. The approach is called DILL (Digital Logic in LOTOS). DILL models are discussed for synchronous and asynchronous circuits. Relations for (strong) conformance are defined for verifying a design specification against a high-level specification. An algorithm is also outlined for generating and applying implementation tests based on a specification. Tools have been developed for automated test generation and verification of conformance between an implementation and its specification. The approach is illustrated with various benchmark circuits as case studies

Formal specification and analysis of digital hardware circuits in LOTOS

SIGLEAvailable from British Library Document Supply Centre-DSC:8723.4018(CSM-158) / BLDSC - British Library Document Supply CentreGBUnited Kingdo

Formal Specification and Analysis of Digital Hardware Circuits in LOTOS

The thesis discusses using ISO standard formal language LOTOS (Language of Temporal Ordering Specification) for formally specifying and analysing digital circuits. The study serves two-fold: it examines the possibility of extending applications of LOTOS outside its traditional areas, and provides a new formalism to aid designing correct hardware. Digital circuits are usually classified into synchronous (clocked) and asynchronous (un-clocked) circuits. The thesis addresses both of them. LOTOS models for signals, wires, components and component connections are established, together with the behavioural models of digital components in synchronous and asynchronous circuits. These formal models help to build the rigorous specifications of digital circuits, which are not only valuable documentation, but also the bases for further analysis. The investigation of the thesis shows that LOTOS is suitable for specifying digital circuits at various levels of abstraction. Compared with oth..