16,874 research outputs found
GPUVerify: A Verifier for GPU Kernels
We present a technique for verifying race- and divergence-freedom of GPU kernels that are written in mainstream ker-nel programming languages such as OpenCL and CUDA. Our approach is founded on a novel formal operational se-mantics for GPU programming termed synchronous, delayed visibility (SDV) semantics. The SDV semantics provides a precise definition of barrier divergence in GPU kernels and allows kernel verification to be reduced to analysis of a sequential program, thereby completely avoiding the need to reason about thread interleavings, and allowing existing modular techniques for program verification to be leveraged. We describe an efficient encoding for data race detection and propose a method for automatically inferring loop invari-ants required for verification. We have implemented these techniques as a practical verification tool, GPUVerify, which can be applied directly to OpenCL and CUDA source code. We evaluate GPUVerify with respect to a set of 163 kernels drawn from public and commercial sources. Our evaluation demonstrates that GPUVerify is capable of efficient, auto-matic verification of a large number of real-world kernels
Engineering a static verification tool for GPU kernels
We report on practical experiences over the last 2.5 years related to the engineering of GPUVerify, a static verification tool for OpenCL and CUDA GPU kernels, plotting the progress of GPUVerify from a prototype to a fully functional and relatively efficient analysis tool. Our hope is that this experience report will serve the verification community by helping to inform future tooling efforts. © 2014 Springer International Publishing
Requirements modelling and formal analysis using graph operations
The increasing complexity of enterprise systems requires a more advanced
analysis of the representation of services expected than is currently possible.
Consequently, the specification stage, which could be facilitated by formal
verification, becomes very important to the system life-cycle. This paper presents
a formal modelling approach, which may be used in order to better represent
the reality of the system and to verify the awaited or existing system’s properties,
taking into account the environmental characteristics. For that, we firstly propose
a formalization process based upon properties specification, and secondly we
use Conceptual Graphs operations to develop reasoning mechanisms of verifying
requirements statements. The graphic visualization of these reasoning enables us
to correctly capture the system specifications by making it easier to determine if
desired properties hold. It is applied to the field of Enterprise modelling
A Hybrid Approach to Formal Verification of Higher-Order Masked Arithmetic Programs
Side-channel attacks, which are capable of breaking secrecy via side-channel
information, pose a growing threat to the implementation of cryptographic
algorithms. Masking is an effective countermeasure against side-channel attacks
by removing the statistical dependence between secrecy and power consumption
via randomization. However, designing efficient and effective masked
implementations turns out to be an error-prone task. Current techniques for
verifying whether masked programs are secure are limited in their applicability
and accuracy, especially when they are applied. To bridge this gap, in this
article, we first propose a sound type system, equipped with an efficient type
inference algorithm, for verifying masked arithmetic programs against
higher-order attacks. We then give novel model-counting based and
pattern-matching based methods which are able to precisely determine whether
the potential leaky observable sets detected by the type system are genuine or
simply spurious. We evaluate our approach on various implementations of
arithmetic cryptographicprograms.The experiments confirm that our approach out
performs the state-of-the-art base lines in terms of applicability, accuracy
and efficiency
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