Feedforward phase noise cancellation exploiting a sub-sampling phase detector

This paper presents a feedforward phase noise cancellation technique to reduce phase noise of the output clock signal of a phase-locked loop (PLL). It uses a sub-sampling phase detector to measure the phase noise and a variable time delay for cancellation. Both phase noise and spurs are reduced. Analytical expressions have been derived that characterize the performance of this technique and show its fundamental limitations. A subsampling phase-locked loop with the cancellation technique as a built-in feature is described. The feedforward technique has no stability requirements in contrast to conventional PLL architectures. The phase noise reduction bandwidth is increased to almost a third of the reference frequency — 3x the maximal bandwidth for 3rd order type-II PLLs. The proposed analytical model shows a phase noise reduction of 9 dB at a frequency offset of fref =10. The total rms jitter is improved by 7.2 dB. The analytical results are verified by simulations

Optimised soft-core processor architecture for noise jamming

M.Ing. (Electrical & Electronic Engineering)Abstract: Noise jamming is a traditional electronic counter measure (ECM) that existed since the establishment of electronic warfare (EW). Traditional noise jamming techniques have been shown to be failing when interacting with intelligent Radar systems such as pulse Doppler radar. Hence there is a need to introduce new noise jamming techniques with digital architecture that will provide improved performance against smart pulse Doppler radar. The work is undertaken to investigate the feasibility of digitizing noise jamming. It focuses on analog-to-digital conversion optimization towards noise jamming architecture, as a result digitization will allow for an opportunity for adaptation of intelligent processing that previously didn’t exist. In this dissertation, certain contributions to the field of noise jamming were made by introducing state of the art odd/even order sampling architecture by proving four case studies. Case study 1 experimentally investigates sample frequency behaviour. Case study 2 uses simulation to investigate step-size and dynamic range behaviour. Case study 3 uses FPGA implementation and SNR to investigate quantization error behaviour. Case study 3 also uses SNR to investigate superiority of proposed odd/even order sampling. Lastly case study 4 uses field measurements, FPGA implementation and SNR to investigate practical implementation of digitized noise jamming. The main contribution is concerned with an architecture that digitizes, reduces sample frequency, optimizes digital resource utilization while reducing noise jamming signal-to-noise ratio. The approach evaluates and empirically compares three sampling techniques from lecture Mod-Δ, Mod-Δ (Gaussian) and Mod-Δ (Sinusoidal) with proposed novel odd/even order sampling. Sampling techniques are evaluated in terms of quantization error, mean square error and signal-to-noise ratio. It was found that the proposed novel odd/even order sampling achieved most case SNR performance of 6 dB in comparison to 18 dB for Mod-Δ. Sampling frequency findings indicated that the proposed novel odd/even order sampling had achieved sampling frequency of 2 kHz in comparison to 8 kHz from traditional 1st order sigma-delta. Dynamic range findings indicated that the proposed odd/even order sampling achieved a dynamic range of 1.088 volts/ms in comparison to 1.185 volts/ms from traditional 1st order sigma-delta. Findings have indicated that the proposed odd/even order sampling has superior SNR and sampling frequency..