4 research outputs found
Frequency characterization of a 2.4 GHz CMOS LNA by Thermal Measurements
© 2006 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a technique to obtain electrical characteristics of analog and RF circuits, based on measuring temperature at the silicon surface close to the circuit under test. Experimental results validate the feasibility of the technique. Simulated results show how this technique can be used to measure the bandwidth and central frequency of a 2.4 GHz low noise amplifier (LNA) designed in a 0.35 microns standard CMOS technology.Peer ReviewedPostprint (published version
High frequency continuous-time circuits and built-in-self-test using CMOS RMS detector
The expanding wireless market has resulted in complex integrated transceivers
that involve RF, analog and mixed-signal circuits, resulting in expensive and complicated
testing. The most important challenges that test engineering faces today are (1) providing
a fast and accurate fault-diagnosis and performance characterization so as to accelerate
the time-to-market and (2) providing an inexpensive test strategy that can be integrated
with the design so as to aid the high-volume manufacturing process. The first part of the
research focuses on the design of an RMS detector for built-in-self-test (BIST) of an RF
integrated transceiver that can directly provide information at various test points in the
design. A cascode low noise amplifier (LNA) has been chosen as the device under test
(DUT). A compact (< 0.031 mm2) RF RMS detector with negligible input capacitance (<
13 fF) has been implemented in 0.35 õm CMOS technology along with the DUT.
Experimental results are currently being assimilated and compared with the simulation
results. Frequency limitations were encountered during the testing process due to
unexpected increase in the value of the N-well resistors. All other problems faced during
the testing, as well as the results obtained so far, are presented in this thesis. In the second part of the research, the use of the RMS detector for BIST has been
extended to a continuous-time high-frequency boost-filter. The proposed HF RMS
detector has been implemented along with a 24 dB 350 MHz boost filter as the DUT on
0.35 õm CMOS technology. The HF RMS detector occupies 0.07 mm2 and has an input
capacitance of 7 fF. The HF RMS detector has a dynamic range greater than 24 dB
starting from -38 dBm of input power. The bandwidth and boost of the filter have been
accurately estimated in simulation using the HF RMS detector. The sensitivity of an
intermediate band pass node of the filter has also been monitored to predict the filter's
sensitivity to Q errors.
The final part of the research describes the design of a single-ended to differential
converter for use in a broadband transceiver operating from 50-850 MHz. This circuit is
used as the second stage in the transceiver after the LNA. The design has been simulated
on a 0.35 um CMOS process and has a power consumption of 13.5 mW and less than 8
dB of noise figure over the entire band. It is capable of driving a 500fF load with less
than 1dB of gain ripple over the entire band (50-850 MHz)
System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits
This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand
(UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits.
The MultiBand OFDM (MB-OFDM) proposal for UWB communications has
received significant attention for the implementation of very high data rate (up to
480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion
quadrature mixer, and the overall radio system-level design are proposed for
an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented
in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with
interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in
quadrature with fast hopping, and a linear phase baseband section with 42dB of gain
programmability. The receiver IC mounted on a FR-4 substrate provides a maximum
gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a
2.5V supply.
Two BIT techniques for analog and RF circuits are developed. The goal is to reduce
the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the
magnitude and phase responses at different nodes of an analog circuit. A complete
prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is
demonstrated by performing frequency response measurements in a range of 1 to
130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF
RMS Detector and a methodology for its use in the built-in measurement of the gain and
1dB compression point of RF circuits are proposed to address the problem of on-chip
testing at RF frequencies. The proposed device generates a DC voltage proportional to
the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology
presents and input capacitance <15fF and occupies and area of 0.03mm2. The application
of these two techniques in combination with a loop-back test architecture significantly
enhances the testability of a wireless transceiver system
Test estructural i predictiu per a circuits RF CMOS
En aquesta tesi s’ha desenvolupat una tècnica de test que permet testar un LNA i un mesclador, situats en el capçal RF d’un receptor CMOS, en una configuració de test semblant al mode normal de funcionament. La circuiteria necessà ria per a implementar aquesta tècnica consta d’un generador IF, per a generar el senyal IF de test, i d’un mesclador auxiliar, per a obtenir el senyal RF de test. Les observables de test escollides han estat l’amplitud de la tensió de sortida del mesclador i el component DC del corrent de consum. S’ha estudiat l’eficà cia de la tècnica de test proposada utilitzant les estratègies de test estructural i predictiu, mitjançant simulacions i mesures experimentals. La seva eficà cia és comparable a altres tècniques de test existents, però l’à rea addicional dedicada a la circuiteria test és inferior.En esta tesis se ha desarrollado una técnica de test que permite verificar un LNA y un mezclador, situados en el cabezal RF de un receptor CMOS, en una configuración de test similar al modo normal de funcionamiento. Los circuitos necesarios para implementar esta técnica son: un generador IF, que permite generar la señal IF de test, y un mezclador auxiliar, para obtener la señal RF de test. Las observables de test seleccionadas han sido la amplitud de la tensión de salida y la componente DC de la corriente de consumo. Se ha estudiado la eficacia de la técnica propuesta usando las estrategias de test estructural y predictiva, mediante simulaciones y medidas experimentales. Su eficacia es comparable a otras técnicas existentes, pero el área dedicada a la circuiteria de test es inferior.This PhD thesis develops a test technique intended for the RF front end of CMOS integrated receivers. This test technique allows testing individually the building blocks of the receiver in a sequential way. The test mode configuration of each block is similar to the normal mode operation. The auxiliary circuitry required to generate the test stimuli consists of an IF generator, which generates the IF test signal, and an auxiliary mixer that produces the RF test signal by mixing the IF test signal with the local oscillator signal. The test observables selected for the test are the voltage amplitude after the IF amplifier, and the DC component of the supply current in each block. The capability of the proposed test technique to perform structural and predictive test strategies has been validated by simulation and experimentally. Its efficiency is comparable to other existing techniques, but the silicon area overhead is lower