Fault-Tolerant Logic Gates Using Neuromorphic CMOS Circuits

Fault-tolerant design methods for VLSI circuits, which have traditionally been addressed at system level, will not be adequate for future very-deep submicron CMOS devices where serious degradation of reliability is expected. Therefore, a new design approach has been considered at low level of abstraction in order to implement robustness and faulttolerance into these devices. Moreover, fault tolerant properties of multi- layer feed-forward artificial neural networks have been demonstrated. Thus, we have implemented this concept at circuit-level, using spiking neurons. Using this approach, the NOT, NAND and NOR Boolean gates have been developed in the AMS 0.35 µm CMOS technology. A very straightforward mapping between the value of a neural weight and one physical parameter of the circuit has also been achieved. Furthermore, the logic gates have been simulated using SPICE corners analysis which emulates manufacturing variations which may cause circuit faults. Using this approach, it can be shown that fault-absorbing neural networks that operate as the desired function can be built

Fault-tolerance of basis function networks using tensor product stabilizers

Eickhoff R, Rückert U. Fault-tolerance of basis function networks using tensor product stabilizers. In: Systems, Man and Cybernetics, 2005 IEEE International Conference on. Vol 3. IEEE; 2005: 2144-2149.Neural networks are intended to be used in future nanoelectronics since these architectures seem to be fault-tolerant to malfunctioning elements and robust to noise. In this paper, the robustness to noise of Basis Function networks using tensor product stabilizers is analyzed and upper bounds of the mean square error under noise contaminated weights or inputs are determined. Furthermore, consequences of permanently malfunctioning neurons are investigated and their impact on the mean squared error is analyzed. To achieve a reliable operation of the neural network necessary restrictions are introduced. Finally, the impact of technical realizations is investigated and its complexity is compared to Radial Basis Functions

Fault-Tolerance of Basis Function Networks Using Tensor Product Stabilizers

Neural networks are intended to be used in future nanoelectronics since these architectures seem to be fault-tolerant to malfunctioning elements and robust to noise. In this paper, the robustness to noise of Basis Function networks using tensor product stabilizers is analyzed and upper bounds of the mean square error under noise contaminated weights or inputs are determined. Furthermore, consequences of permanently malfunctioning neurons are investigated and their impact on the mean squared error is analyzed. To achieve a reliable operation of the neural network necessary restrictions are introduced. Finally, the impact of technical realizations is investigated and its complexity is compared to Radial Basis Functions

Fehlertolerante neuronale Netze zur Approximation von Funktionen

Tag der Verteidigung: 11.07.2007Paderborn, Univ., Diss., 200