5 research outputs found
Statistical static timing analysis considering the impact of power supply noise in VLSI circuits
As semiconductor technology is scaled and voltage level is reduced, the impact
of the variation in power supply has become very significant in predicting the realistic
worst-case delays in integrated circuits. The analysis of power supply noise is inevitable
because high correlations exist between supply voltage and delay. Supply noise analysis
has often used a vector-based timing analysis approach. Finding a set of test vectors in
vector-based approaches, however, is very expensive, particularly during the design
phase, and becomes intractable for larger circuits in DSM technology.
In this work, two novel vectorless approaches are described such that increases
in circuit delay, because of power supply noise, can be efficiently, quickly estimated.
Experimental results on ISCAS89 circuits reveal the accuracy and efficiency of my
approaches: in s38417 benchmark circuits, errors on circuit delay distributions are less
than 2%, and both of my approaches are 67 times faster than the traditional vector-based
approach. Also, the results show the importance of considering care-bits, which sensitize
the longest paths during the power supply noise analysis
Empirical timing analysis of CPUs and delay fault tolerant design using partial redundancy
The operating clock frequency is determined by the longest signal propagation
delay, setup/hold time, and timing margin. These are becoming less predictable with
the increasing design complexity and process miniaturization. The difficult challenge
is then to ensure that a device operating at its clock frequency is error-free with
quantifiable assurance. Effort at device-level engineering will not suffice for these
circuits exhibiting wide process variation and heightened sensitivities to operating
condition stress. Logic-level redress of this issue is a necessity and we propose a
design-level remedy for this timing-uncertainty problem.
The aim of the design and analysis approaches presented in this dissertation is to
provide framework, SABRE, wherein an increased operating clock frequency can be
achieved. The approach is a combination of analytical modeling, experimental analy-
sis, hardware /time-redundancy design, exception handling and recovery techniques.
Our proposed design replicates only a necessary part of the original circuit to avoid
high hardware overhead as in triple-modular-redundancy (TMR). The timing-critical
combinational circuit is path-wise partitioned into two sections. The combinational
circuits associated with long paths are laid out without any intrusion except for the
fan-out connections from the first section of the circuit to a replicated second section
of the combinational circuit. Thus only the second section of the circuit is replicated.
The signals fanning out from the first section are latches, and thus are far shorter than the paths spanning the entire combinational circuit. The replicated circuit is timed
at a subsequent clock cycle to ascertain relaxed timing paths. This insures that the
likelihood of mistiming due to stress or process variation is eliminated. During the
subsequent clock cycle, the outcome of the two logically identical, yet time-interleaved,
circuit outputs are compared to detect faults. When a fault is detected, the retry sig-
nal is triggered and the dynamic frequency-step-down takes place before a pipe flush,
and retry is issued. The significant timing overhead associated with the retry is offset
by the rarity of the timing violation events. Simulation results on ISCAS Benchmark
circuits show that 10% of clock frequency gain is possible with 10 to 20 % of hardware
overhead of replicated timing-critical circuit