3,849 research outputs found
Synthesis and Optimization of Reversible Circuits - A Survey
Reversible logic circuits have been historically motivated by theoretical
research in low-power electronics as well as practical improvement of
bit-manipulation transforms in cryptography and computer graphics. Recently,
reversible circuits have attracted interest as components of quantum
algorithms, as well as in photonic and nano-computing technologies where some
switching devices offer no signal gain. Research in generating reversible logic
distinguishes between circuit synthesis, post-synthesis optimization, and
technology mapping. In this survey, we review algorithmic paradigms ---
search-based, cycle-based, transformation-based, and BDD-based --- as well as
specific algorithms for reversible synthesis, both exact and heuristic. We
conclude the survey by outlining key open challenges in synthesis of reversible
and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table
Low Power Reversible Parallel Binary Adder/Subtractor
In recent years, Reversible Logic is becoming more and more prominent
technology having its applications in Low Power CMOS, Quantum Computing,
Nanotechnology, and Optical Computing. Reversibility plays an important role
when energy efficient computations are considered. In this paper, Reversible
eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design
III are proposed. In all the three design approaches, the full Adder and
Subtractors are realized in a single unit as compared to only full Subtractor
in the existing design. The performance analysis is verified using number
reversible gates, Garbage input/outputs and Quantum Cost. It is observed that
Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is
efficient compared to Design I, Design II and existing design.Comment: 12 pages,VLSICS Journa
DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction
Recently much attention has been paid to quantum circuit design to prepare
for the future "quantum computation era." Like the conventional logic
synthesis, it should be important to verify and analyze the functionalities of
generated quantum circuits. For that purpose, we propose an efficient
verification method for quantum circuits under a practical restriction. Thanks
to the restriction, we can introduce an efficient verification scheme based on
decision diagrams called
Decision Diagrams for Matrix Functions (DDMFs). Then, we show analytically
the advantages of our approach based on DDMFs over the previous verification
techniques. In order to introduce DDMFs, we also introduce new concepts,
quantum functions and matrix functions, which may also be interesting and
useful on their own for designing quantum circuits.Comment: 15 pages, 14 figures, to appear IEICE Trans. Fundamentals, Vol.
E91-A, No.1
Fast equivalence checking of quantum circuits of Clifford gates
Checking whether two quantum circuits are equivalent is important for the
design and optimization of quantum-computer applications with real-world
devices. We consider quantum circuits consisting of Clifford gates, a
practically-relevant subset of all quantum operations which is large enough to
exhibit quantum features such as entanglement and forms the basis of, for
example, quantum-error correction and many quantum-network applications. We
present a deterministic algorithm that is based on a folklore mathematical
result and demonstrate that it is capable of outperforming previously
considered state-of-the-art method. In particular, given two Clifford circuits
as sequences of single- and two-qubit Clifford gates, the algorithm checks
their equivalence in time in the number of qubits and number
of elementary Clifford gates . Using the performant Stim simulator as
backend, our implementation checks equivalence of quantum circuits with 1000
qubits (and a circuit depth of 10.000 gates) in 22 seconds and circuits
with 100.000 qubits (depth 10) in 15 minutes, outperforming the existing
SAT-based and path-integral based approaches by orders of magnitude. This
approach shows that the correctness of application-relevant subsets of quantum
operations can be verified up to large circuits in practice
Verifying Results of the IBM Qiskit Quantum Circuit Compilation Flow
Realizing a conceptual quantum algorithm on an actual physical device
necessitates the algorithm's quantum circuit description to undergo certain
transformations in order to adhere to all constraints imposed by the hardware.
In this regard, the individual high-level circuit components are first
synthesized to the supported low-level gate-set of the quantum computer, before
being mapped to the target's architecture---utilizing several optimizations in
order to improve the compilation result. Specialized tools for this complex
task exist, e.g., IBM's Qiskit, Google's Cirq, Microsoft's QDK, or Rigetti's
Forest. However, to date, the circuits resulting from these tools are hardly
verified, which is mainly due to the immense complexity of checking if two
quantum circuits indeed realize the same functionality. In this paper, we
propose an efficient scheme for quantum circuit equivalence
checking---specialized for verifying results of the IBM Qiskit quantum circuit
compilation flow. To this end, we combine characteristics unique to quantum
computing, e.g., its inherent reversibility, and certain knowledge about the
compilation flow into a dedicated equivalence checking strategy. Experimental
evaluations confirm that the proposed scheme allows to verify even large
circuit instances with tens of thousands of operations within seconds or even
less, whereas state-of-the-art techniques frequently time-out or require
substantially more runtime. A corresponding open source implementation of the
proposed method is publicly available at https://github.com/iic-jku/qcec.Comment: 10 pages, to be published at International Conference on Quantum
Computing and Engineering (QCE20
- …