Fast And Accurate Solution For Power Estimation And Dpa Countermeasure Design

Power and energy consumption is a major issue and a design constraint in many types of systems. However, the knowledge of average power consumption is not enough, since many issues may arise due to dynamic power characteristics, such as IR drop, and side channel attacks in cryptographic circuits via DPA. Analog simulation (e.g. Spice), which has been used for decades as an accurate mean for estimating current and power, is no longer an option when it comes to medium to large circuits, due to the unacceptable simulation time. This paper presents an open framework for fast and accurate dynamic power estimation based on gate-level simulation, and standard tools and libraries. Our solution was thoroughly evaluated using standard benchmark and cryptographic circuits. Relevant speed and accuracy measures were compared to the ones obtained with analog simulation, such as speed-up, peak and average power, and cross correlation. A comparison with other published solutions was conducted, when possible. Our solution achieved a speed-up of three orders of magnitude in simulation time as compared to analog simulation, which is one order of magnitude better than other published solutions. The results, such as average and peak power and correlation, are in the same range as the published solutions. When applied to cryptographic circuits our solution has shown similar results to benchmark circuits indicating a feasible solution for DPA evaluation usage. Our solution is totally based on standard simulators and libraries. It is fully open and it has disclosed documentation and code, available for public use.Weste, N., Harris, D., (2011) CMOS VLSI Design: A Circuits and Systems Perspective, , ADDISON WESLEY Publishing Company IncorporatedBernardi, P., De Carvalho, M., Sanchez, E., Reorda, M., Bosio, A., Dilillo, L., Girard, P., Valka, M., Peak power estimation: A case study on cpu cores (2012) IEEE Asian Test Symp., pp. 167-172Mangard, S., Oswald, E., Popp, T., (2008) Power Analysis Attacks: Revealing the Secrets of Smart Cards, , ser. Advances in information security. Springer Science+Business Media, LLCRewieński, M., A perspective on fast-spice simulation technology (2011) Simulation and Verification of Electronic and Biological Systems, pp. 23-42. , Springer(2013) Open Source Liberty Website, , http://www.opensourceliberty.org, Retrieved: 2014-06-06. [Online](2001) Verilog Hardware Description Language, pp. 0-856. , IEEE, IEEE Std 1364-2001Di Natale, G., Flottes, M.-L., Rouzeyre, B., An integrated validation environment for differential power analysis (2008) IEEE Int. Symp. on Electronic Design, Test and Applications, DELTA 2008, pp. 527-532. , JanSmith, K., Łukowiak, M., Methodology for simulated power analysis attacks on aes (2010) Military Commun. Conf., MILCOM 2010, pp. 1292-1297. , Oct(2013) Prime Time PX, , www.synopsys.com, Retrieved: 2014-06-06. [Online](2012) Encounter Power System Datasheet, , www.cadence.com, Retrieved: 2014-06-06. [Online]Cirit, M.A., (2004) Powerteam™: There is More to Verilog beyond Behavioral SimulationKrodel, T., Power play-fast dynamic power estimation based on logic simulation (1991) IEEE Int. Conf. on Computer Design: VLSI in Computers and Processors, ICCD '91, pp. 96-100Bogliolo, A., Benini, L., De Micheli, G., Ricco, B., Gate-level power and current simulation of cmos integrated circuits (1997) IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 5 (4), pp. 473-488Lee, M.-S., Lin, C.-H., Liu, C.-N.J., Lin, S.-C., Quick supply current waveform estimation at gate level using existed cell library information (2008) Proc. of the 18th ACM Great Lakes Symp. on VLSI, pp. 135-138. , ser. GLSVLSI '08. New York, NY, USA: ACMVidal, D., Côrtes, M., FDPE (Fast and accurate dynamic power estimation): Implementation and user guidelines Inst. of Computing, UNICAMP, Tech. Rep., , To be publishedBracewell, R., Pentagram notation for cross correlation (1965) The Fourier Transform and Its Applications, pp. 46-243. , New York: McGraw-HillBrglez, F., Fujiwara, H., A neutral netlist of 10 combinational benchmark circuits (1985) IEEE Int. Symp. on Circuits and Systems, pp. 695-698Brglez, F., Bryan, D., Kozminski, K., Combinational profiles of sequential benchmark circuits (1989) IEEE Int. Symp. on Circuits and Systems, 3, pp. 1929-193