Hardware Simulation Tools for ARM Architectures

RESUMEN: El vertiginoso avance de la tecnología, soportado en gran medida por los recursos de computación disponibles, convierte su estudio y desarrollo en un área de investigación fundamental. Dado el actual nivel de complejidad de cualquier procesador comercial, esta tarea se ha vuelto extremadamente complicada. Evaluar nuevas alternativas para mejorar las cotas de rendimiento de un procesador supone un gran esfuerzo de investigación, siendo el coste de “prototipado” hardware inasumible cada vez que se requiere poner a prueba una posible modificación. Debido a esta limitación surge la simulación por software que, esencialmente, consiste en emular el hardware a través de un programa, permitiendo al usuario observar el comportamiento de un sistema que no necesariamente exista. Esta metodología evita disponer de un prototipo cada vez que se requiera evaluar un cambio en el procesador. A pesar de sus evidentes ventajas, el proceso de simulación de sistema completo es complejo y tedioso. Para obtener resultados con un nivel de precisión razonable y una funcionalidad adecuada, es preciso un trabajo previo con las herramientas de simulación que dista de ser trivial. El objetivo principal del presente Trabajo de Fin de Grado ha consistido en desplegar un simulador de sistema completo sobre la plataforma de desarrollo Nvidia Jetson TX21, preparándolo para simular una arquitectura ARM (actualmente en auge). Las tareas principales realizadas durante el proyecto han consistido en el despliegue e instalación de la plataforma de trabajo (Jetson TX2), la instalación del simulador Gem5 preparado para desarrollar sobre una arquitectura ARM, la puesta a punto tanto del kernel de la máquina como del framework de simulación para poder hacer uso de las extensiones de virtualización propias del ISA del procesador (agilizando de manera muy significativa el proceso de simulación) y la evaluación del working-set de varias aplicaciones pertenecientes a la suite de benchmarks SPEC CPU2017.ABSTRACT: The huge advances on technology, mostly driven by available computing resources, makes its study and development a fundamental research area. Given the current level of complexity of any commercial processor, this task has become increasingly complicated. Testing new possibilities to improve performance levels involves a great deal on research, the cost of hardware prototyping being unbearable each time a possible modification is required to be tested. Due to this limitation, software simulation arises. This essentially consists of a program that allows the user to observe the behavior of a system that does not necessarily exist. This process would avoid having a prototype every time a change is required. Despite its obvious advantages, the complete system simulation process is complex and tedious. In order to obtain results with a reasonable level of precision and adequate functionality, it is necessary to work previously on the simulation tools, which is far from trivial. The main objective of this End of Grade Project consists on deploying a complete system simulator on the development platform Nvidia Jetson TX2, adapting it to simulate an ARM architecture (now in its peak). The main tasks carried out during the project have consisted in the deployment and installation of the working platform (Jetson TX2)2, the installation of the Gem5 simulator (including the build process that allows to develop on ARM), the fine-tuning of both the machine kernel and the simulation framework to be able to make use of the virtualization extensions of the processor's ISA (significantly speeding up the simulation process) and the evaluation of the working-set of several applications belonging to the SPEC CPU2017 benchmarks suite.Grado en Ingeniería Informátic

Fast and accurate branch predictor simulation

International audienceThe complexity of embedded processors has raised dramatically, due to the addition of architectural add-ons which improve performances significantly. High level models used in system simulation usually ignore these additions as the major issue is functional correctness. However, accurate estimates of software execution is sometimes required, therefore we focus in this paper on one of theses architectural features, the branch predictor. Unfortunately, advanced branch predictors use large tables, so that models directly implementing these schemes slow down simulation dramatically. To limit the simulation overhead, we define a modeling approach that we demonstrate on a state of the art predictor. We implemented the model in a dynamic binary translation based instruction set simulator and measured an accuracy of prediction of about 95% for a run-time overhead of less than 5%