Parametric, Secure and Compact Implementation of RSA on FPGA

We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The design utilizes dedicated block multipliers as the main functional unit and Block-RAM as storage unit for the operands. The adopted design methodology allows adjusting the number of multipliers, the radix used in the multipliers, and number of words to meet the system requirements such as available resources, precision and timing constraints. The architecture, based on the Montgomery modular multiplication algorithm, utilizes a pipelining technique that allows concurrent operation of hardwired multipliers. Our design completes 1020-bit and 2040-bit modular multiplications in 7.62 μs and 27.0 μs, respectively. The multiplier uses a moderate amount of system resources while achieving the best area-time product in literature. 2040-bit modular exponentiation engine can easily fit into Xilinx Spartan-3E 500; moreover the exponentiation circuit withstands known side channel attacks

Advances in Thick GEM-like gaseous electron multipliers. Part I: atmospheric pressure operation

Thick GEM-like (THGEM) gaseous electron multipliers are made of standard printed-circuit board perforated with sub-millimeter diameter holes, etched at their rims. Effective gas multiplication factors of 100000 and 10000000 and fast pulses in the few nanosecond rise-time scale were reached in single- and cascaded double-THGEM elements, in atmospheric-pressure standard gas mixtures with single photoelectrons. High single-electron detection efficiency is obtained in photon detectors combining THGEMs and semitransparent UV-sensitive CsI photocathodes or reflective ones deposited on the top THGEM face; the latter benefits of a reduced sensitivity to ionizing background radiation. Stable operation was recorded with photoelectron fluxes exceeding MHz/mm2. The properties and some potential applications of these simple and robust multipliers are discussed.Comment: 41 pages, 27 figures. Submitted to Nucl. Instr. and Meth. A, Dec 21, 200

FPGA Implementation & Performance Comparision of Various High Speed unsigned Binary Multipliers using VHDL

Today, most of the DSP computations involve the use of multiply accumulate operations and therefore the design of fast and efficient multipliers is imperative. The addition and multiplication of two binary numbers is the fundamental and most often used arithmetic operation in microprocessors, digital signal processors and data-processing application-specific integrated circuits. In this paper, we present the study of different types of multipliers by comparing the speed and area of each. In this work, VHDL coding and XILINX ISE Simulator is employed to implement multipliers like WTM, Dadda Multiplier, Vedic Multiplier, CSHM, Serial Multiplier and Multipliers using different compressors in Wallace tree architecture. The analysis of this work would be helpful to choose a better multiplier in order to fabricate an efficient system