8,814 research outputs found
Automatic generation of hardware Tree Classifiers
Machine Learning is growing in popularity and spreading across different fields for various applications. Due to this trend, machine learning algorithms use different hardware platforms and are being experimented to obtain high test accuracy and throughput. FPGAs are well-suited hardware platform for machine learning because of its re-programmability and lower power consumption. Programming using FPGAs for machine learning algorithms requires substantial engineering time and effort compared to software implementation. We propose a software assisted design flow to program FPGA for machine learning algorithms using our hardware library. The hardware library is highly parameterized and it accommodates Tree Classifiers. As of now, our library consists of the components required to implement decision trees and random forests. The whole automation is wrapped around using a python script which takes you from the first step of having a dataset and design choices to the last step of having a hardware descriptive code for the trained machine learning model
Development and implementation of a LabVIEW based SCADA system for a meshed multi-terminal VSC-HVDC grid scaled platform
This project is oriented to the development of a Supervisory, Control and Data Acquisition
(SCADA) software to control and supervise electrical variables from a scaled platform that
represents a meshed HVDC grid employing National Instruments hardware and LabVIEW logic
environment. The objective is to obtain real time visualization of DC and AC electrical variables
and a lossless data stream acquisition.
The acquisition system hardware elements have been configured, tested and installed on the
grid platform. The system is composed of three chassis, each inside of a VSC terminal cabinet,
with integrated Field-Programmable Gate Arrays (FPGAs), one of them connected via PCI bus
to a local processor and the rest too via Ethernet through a switch. Analogical acquisition
modules were A/D conversion takes place are inserted into the chassis. A personal computer is
used as host, screen terminal and storing space.
There are two main access modes to the FPGAs through the real time system. It has been
implemented a Scan mode VI to monitor all the grid DC signals and a faster FPGA access mode
VI to monitor one converter AC and DC values. The FPGA application consists of two tasks
running at different rates and a FIFO has been implemented to communicate between them
without data loss.
Multiple structures have been tested on the grid platform and evaluated, ensuring the
compliance of previously established specifications, such as sampling and scanning rate, screen
refreshment or possible data loss.
Additionally a turbine emulator was implemented and tested in Labview for further testing
Evaluation of Single-Chip, Real-Time Tomographic Data Processing on FPGA - SoC Devices
A novel approach to tomographic data processing has been developed and
evaluated using the Jagiellonian PET (J-PET) scanner as an example. We propose
a system in which there is no need for powerful, local to the scanner
processing facility, capable to reconstruct images on the fly. Instead we
introduce a Field Programmable Gate Array (FPGA) System-on-Chip (SoC) platform
connected directly to data streams coming from the scanner, which can perform
event building, filtering, coincidence search and Region-Of-Response (ROR)
reconstruction by the programmable logic and visualization by the integrated
processors. The platform significantly reduces data volume converting raw data
to a list-mode representation, while generating visualization on the fly.Comment: IEEE Transactions on Medical Imaging, 17 May 201
Scalable Interactive Volume Rendering Using Off-the-shelf Components
This paper describes an application of a second generation implementation of the Sepia architecture (Sepia-2) to interactive volu-metric visualization of large rectilinear scalar fields. By employingpipelined associative blending operators in a sort-last configuration a demonstration system with 8 rendering computers sustains 24 to 28 frames per second while interactively rendering large data volumes (1024x256x256 voxels, and 512x512x512 voxels). We believe interactive performance at these frame rates and data sizes is unprecedented. We also believe these results can be extended to other types of structured and unstructured grids and a variety of GL rendering techniques including surface rendering and shadow map-ping. We show how to extend our single-stage crossbar demonstration system to multi-stage networks in order to support much larger data sizes and higher image resolutions. This requires solving a dynamic mapping problem for a class of blending operators that includes Porter-Duff compositing operators
Data acquisition electronics and reconstruction software for directional detection of Dark Matter with MIMAC
Directional detection of galactic Dark Matter requires 3D reconstruction of
low energy nuclear recoils tracks. A dedicated acquisition electronics with
auto triggering feature and a real time track reconstruction software have been
developed within the framework of the MIMAC project of detector. This
auto-triggered acquisition electronic uses embedded processing to reduce data
transfer to its useful part only, i.e. decoded coordinates of hit tracks and
corresponding energy measurements. An acquisition software with on-line
monitoring and 3D track reconstruction is also presented.Comment: 17 pages, 12 figure
ACE 16k based stand-alone system for real-time pre-processing tasks
This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The system's architecture has been implemented and tested using an ACE16k chip and a Xilinx xc4028xl FPGA. The ACE16k chip consists basically of an array of 128×128 identical mixed-signal processing units, locally interacting, which operate in accordance with single instruction multiple data (SIMD) computing architectures and has been designed for high speed image pre-processing tasks requiring moderate accuracy levels (7 bits). The input images are acquired using the optical input capabilities of the ACE16k chip, and after being processed according to a programmed algorithm, the images are represented at real time on a TFT screen. The system is designed to store and run different algorithms and to allow changes and improvements. Its main board includes a digital core, implemented on a Xilinx 4028 Series FPGA, which comprises a custom programmable Control Unit, a digital monochrome PAL video generator and an image memory selector. Video SRAM chips are included to store and access images processed by the ACE16k. Two daughter boards hold the program SRAM and a video DAC-mixer card is used to generate composite analog video signal.European Commission IST2001 – 38097Ministerio de Ciencia y Tecnología TIC2003 – 09817- C02 – 01Office of Naval Research (USA) N00014021088
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