1,450 research outputs found
A Hardware Implementation of Artificial Neural Network Using Field Programmable Gate Arrays
An artificial neural network algorithm is implemented using a field
programmable gate array hardware. One hidden layer is used in the feed-forward
neural network structure in order to discriminate one class of patterns from
the other class in real time. With five 8-bit input patterns, six hidden nodes,
and one 8-bit output, the implemented hardware neural network makes decision on
a set of input patterns in 11 clocks and the result is identical to what to
expect from off-line computation. This implementation may be used in level 1
hardware triggers in high energy physics experimentsComment: 13 pages, 4 figures, submitted to Nucl. Instr. Meth.
FPGA Implementation of Convolutional Neural Networks with Fixed-Point Calculations
Neural network-based methods for image processing are becoming widely used in
practical applications. Modern neural networks are computationally expensive
and require specialized hardware, such as graphics processing units. Since such
hardware is not always available in real life applications, there is a
compelling need for the design of neural networks for mobile devices. Mobile
neural networks typically have reduced number of parameters and require a
relatively small number of arithmetic operations. However, they usually still
are executed at the software level and use floating-point calculations. The use
of mobile networks without further optimization may not provide sufficient
performance when high processing speed is required, for example, in real-time
video processing (30 frames per second). In this study, we suggest
optimizations to speed up computations in order to efficiently use already
trained neural networks on a mobile device. Specifically, we propose an
approach for speeding up neural networks by moving computation from software to
hardware and by using fixed-point calculations instead of floating-point. We
propose a number of methods for neural network architecture design to improve
the performance with fixed-point calculations. We also show an example of how
existing datasets can be modified and adapted for the recognition task in hand.
Finally, we present the design and the implementation of a floating-point gate
array-based device to solve the practical problem of real-time handwritten
digit classification from mobile camera video feed
Implementation of Efficient Multilayer Perceptron ANN Neurons on Field Programmable Gate Array Chip
Artificial Neural Network is widely used to learn data from systems for different types of applications. The capability of different types of Integrated Circuit (IC) based ANN structures also depends on the hardware backbone used for their implementation. In this work, Field Programmable Gate Array (FPGA) based Multilayer Perceptron Artificial Neural Network (MLP-ANN) neuron is developed. Experiments were carried out to demonstrate the hardware realization of the artificial neuron using FPGA. Two different activation functions (i.e. tan-sigmoid and log-sigmoid) were tested for the implementation of the proposed neuron. Simulation result shows that tan-sigmoid with a high index (i.e. k >= 40) is a better choice of sigmoid activation function for the harware implemetation of a MLP-ANN neuron
Implementing Neural Network-Based Equalizers in a Coherent Optical Transmission System Using Field-Programmable Gate Arrays
In this work, we demonstrate the offline FPGA realization of both recurrent
and feedforward neural network (NN)-based equalizers for nonlinearity
compensation in coherent optical transmission systems. First, we present a
realization pipeline showing the conversion of the models from Python libraries
to the FPGA chip synthesis and implementation. Then, we review the main
alternatives for the hardware implementation of nonlinear activation functions.
The main results are divided into three parts: a performance comparison, an
analysis of how activation functions are implemented, and a report on the
complexity of the hardware. The performance in Q-factor is presented for the
cases of bidirectional long-short-term memory coupled with convolutional NN
(biLSTM + CNN) equalizer, CNN equalizer, and standard 1-StpS digital
back-propagation (DBP) for the simulation and experiment propagation of a
single channel dual-polarization (SC-DP) 16QAM at 34 GBd along 17x70km of LEAF.
The biLSTM+CNN equalizer provides a similar result to DBP and a 1.7 dB Q-factor
gain compared with the chromatic dispersion compensation baseline in the
experimental dataset. After that, we assess the Q-factor and the impact of
hardware utilization when approximating the activation functions of NN using
Taylor series, piecewise linear, and look-up table (LUT) approximations. We
also show how to mitigate the approximation errors with extra training and
provide some insights into possible gradient problems in the LUT approximation.
Finally, to evaluate the complexity of hardware implementation to achieve 400G
throughput, fixed-point NN-based equalizers with approximated activation
functions are developed and implemented in an FPGA.Comment: Invited paper at Journal of Lightwave Technology - IEE
- …