High-Performance Parallel Implementation of Genetic Algorithm on FPGA

Genetic algorithms (GAs) are used to solve search and optimization problems in which an optimal solution can be found using an iterative process with probabilistic and non-deterministic transitions. However, depending on the problem’s nature, the time required to find a solution can be high in sequential machines due to the computational complexity of genetic algorithms. This work proposes a full-parallel implementation of a genetic algorithm on field-programmable gate array (FPGA). Optimization of the system’s processing time is the main goal of this project. Results associated with the processing time and area occupancy (on FPGA) for various population sizes are analyzed. Studies concerning the accuracy of the GA response for the optimization of two variables functions were also evaluated for the hardware implementation. However, the high-performance implementation proposed in this paper is able to work with more variable from some adjustments on hardware architecture. The results showed that the GA full-parallel implementation achieved throughput about 16 millions of generations per second and speedups between 17 and 170,000 associated with several works proposed in the literature

Flexible implementation of genetic algorithms on FPGAs

FPGA '06 : ACM/SIGDA 14th international symposium on Field programmable gate arrays , Feb 22-24, 2006 , Monterey, CA, USAGenetic algorithms (GAs) are useful since they can find near optimal solutions for combinatorial optimization problems quickly. Although there are many mobile/home applications of GAs such as navigation systems, QoS routing and video encoding systems, it was difficult to apply GAs to those applications due to low computational power of mobile/home appliances. In this paper, we propose a technique to flexibly implement genetic algorithms for various problems on FPGAs. For the purpose, we propose a basic architecture which consists of several modules for GA operations to compose a GA pipeline, and a parallel architecture consisting of multiple concurrent pipelines. The proposed architectures are simple enough to be implemented on FPGAs, applicable to various problems, and easy to estimate the size of the resulting circuit. We also propose a model for predicting the size of resulting circuit from given parameters consisting of the problem size, the number of concurrent pipelines and the number of candidate solutions for GA. Based on the proposed method, we have implemented a tool to facilitate GA circuit design and development. This tool allows designers to find appropriate parameter values so that the resulting circuit can be accommodated in the target FPGA device, and to automatically obtain RTL VHDL description. Through experiments using Knapsack Problem and TSP, we show that the FPGA circuits synthesized based on the proposed method run much faster and consume much lower power than software implementation on a PC and that our model can predict the size of the resulting circuit accurately enough

A Hardware Implementation Method of Multi-Objective Genetic Algorithms

CEC2006 : IEEE International Conference on Evolutionary Computation , Jul 16-21, 2006 , Vancouver, BC, CanadaMulti-objective genetic algorithms (MOGAs) are approximation techniques to solve multi-objective optimization problems. Since MOGAs search a wide variety of pareto optimal solutions at the same time, MOGAs require large computation power. In order to solve practical sizes of the multi objective optimization problems, it is desirable to design and develop a hardware implementation method for MOGAs with high search efficiency and calculation speed. In this paper, we propose a new method to easily implement MOGAs as high performance hardware circuits. In the proposed method, we adopt simple Minimal Generation Gap (MGG) model as the generation model, because it is easy to be pipelined. In order to preserve diversity of individuals, we need a special selection mechanism such as the niching method which takes large computation time to repeatedly compare superiority among all individuals in the population. In the proposed method, we developed a new selection mechanism which greatly reduces the number of comparisons among individuals, keeping diversity of individuals. Our method also includes a parallel execution architecture based on Island GA which is scalable to the number of concurrent pipelines and effective to keep diversity of individuals. We applied our method to multi-objective Knapsack Problem. As a result, we confirmed that our method has higher search efficiency than existing method

Implementation of Genetic Algorithms in FPGA-based Reconfigurable Computing Systems

Genetic Algorithms (GAs) are used to solve many optimization problems in science and engineering. GA is a heuristics approach which relies largely on random numbers to determine the approximate solution of an optimization problem. We use the Mersenne Twister Algorithm (MTA) to generate a non-overlapping sequence of random numbers with a period of 219937-1. The random numbers are generated from a state vector that consists of 624 elements. Our work on state vector generation and the GA implementation targets the solution of a flow-line scheduling problem where the flow-lines have jobs to process and the goal is to find a suitable completion time for all jobs using a GA. The state vector generation algorithm (MTA) performs poorly in traditional von Neumann architectures due to its poor temporal and spatial locality. Therefore its performance is limited by the speed at which we can access memory. With an approximate increase of processor performance by 60% per year and a drop of memory latency only 7% per year, a new approach is needed for performance improvement. On the other hand, the GA implementation in a general-purpose microprocessor, though performs reasonably well, has scope for performance gain in a parallel implementation. The parallel implementation of the GA can work as a kernel for applications that uses a GA to reach a solution. Our approach is to implement the state vector generation process and the GA in an FPGA-based Reconfigurable Computing (RC) system with the goal of improving the overall performance. Application design for FPGA-based RC systems is not trivial and the performance improvement is not guaranteed. Designing for RC systems requires algorithmic parallelism in order to exploit the inherent parallelism of the FPGA. We are using a high-level language that provides a level of abstraction from the lower-level hardware in the RC system making it difficult to fully exploit some of the architectural benefits of the FPGA. Considering these factors, we improve the state vector generation process algorithmically. Our implementation generates state vectors 5X faster than the previous implementation in an Intel Xeon microprocessor of 2GHz. The modified algorithm is also implemented in a Xilinx Virtex-4 FPGA that results in a 2.4X speedup. Improvement in this preprocessing step accelerates GA application performance as random numbers are generated from these state vectors for the genetic operators. We simulate the basic operations of a GA in an FPGA to study its behavior in a parallel environment and analyze the results. The initial FPGA implementation of the GA runs about 7X slower than its microprocessor counterpart. The reasons are explained along with suggestions for improvement and future work

Implementation of Genetic Algorithms on an FPGA Ethernet Tester

In electrical substation automation systems (SAS), intelligent electronic devices (IED) communicate over Ethernet within the IEC 61850 standard. The main objective of the standard is to bring compatibility, security and robustness between different IEDs, regardless the manufacturer. A typical SAS consists of IEDs such as circuit breakers, protection relays and controllers. This thesis concerns the generation and transmission of Ethernet traffic from a Field Programmable Gate Array (FPGA) to an IED. The research question was to study the robustness of the IEC 61580 standard implementation on an IED and search for Ethernet data that might be harmful for the device. An FPGA, with high speed performance due to its parallelism, combined with a genetic algorithm search optimization process, was chosen to approach the problem. Genetic algorithms are optimization methods which have taken inspiration from biology, where species strive for survival. In this research case, genetic algorithms were implemented in an FPGA where they are adapted to the Ethernet frames by means of recombination and mutation of binary data. Transmission-round trip time feedbacks were measured by an external device, where a larger transmission time results in a greater fitness value, gaining a higher probability of finding harmful data. The result was a hardware implementation of genetic algorithms on an FPGA platform that manages to transmit Ethernet frames at high speed. In the research it was also obtained that it is possible to cause an IED to crash depending on Ethernet frame data and transmission speed.fi=Opinnäytetyö kokotekstinä PDF-muodossa.|en=Thesis fulltext in PDF format.|sv=Lärdomsprov tillgängligt som fulltext i PDF-format

Implementation of genetic algorithm based fuzzy logic controller with automatic rule extraction in FPGA

A number of fuzzy logic controllers are being designed till now to replace complex, non-linear and huge controlling equipment in numerous industrial sectors. But the designing of these controllers requires thorough knowledge about the controlled process. For this purpose a highly experienced experts are required, which is not feasible all the time. Most of these processes are non-linear and depend on large number of parameters. Thus mathematical representation of these systems is an arduous line of work. This project addresses these problems by proposing using of genetic algorithm based Fuzzy Logic systems as controllers. The system includes algorithms which are run on a capable computing platform, to read an experimental data sheet obtained from experimental observations of the system and generate a fine tuned rule base that is to be used in the fuzzy logic controller hardware. The hardware is implemented in an FPGA. Transfer of synthesized rule base from the computer to the FPGA implementation and crisp output value back to the computer is done by UART. A graphical user interface is provided that runs on the computer