Dynamical attractors of memristors and their networks

It is shown that the time-averaged dynamics of memristors and their networks periodically driven by alternating-polarity pulses may converge to fixed-point attractors. Starting with a general memristive system model, we derive basic equations describing the fixed-point attractors and investigate attractors in the dynamics of ideal, threshold-type and second-order memristors, and memristive networks. A memristor potential function is introduced, and it is shown that in some cases the attractor identification problem can be mapped to the problem of potential function minimization. Importantly, the fixed-point attractors may only exist if the function describing the internal state dynamics depends on an internal state variable. Our findings may be used to tune the states of analog memristors, and also be relevant to memristive synapses subjected to forward- and back-propagating spikes

Exploring the voltage divider approach for accurate memristor state tuning

The maximum exploitation of the favorable properties and the analog nature of memristor technology in future nonvolatile resistive memories, requires accurate multilevel programming. In this direction, we explore the voltage divider (VD) approach for highly controllable multi-state SET memristor tuning. We present the theoretical basis of operation, the main advantages and weaknesses. We finally propose an improved closed-loop VD SET scheme to tackle the variability effect and achieve <1% tuning precision, on average 3× faster than another accurate tuning algorithm of the recent literature.Peer ReviewedPostprint (published version

Exploring the voltage divider approach for accurate memristor state tuning

The maximum exploitation of the favorable properties and the analog nature of memristor technology in future nonvolatile resistive memories, requires accurate multilevel programming. In this direction, we explore the voltage divider (VD) approach for highly controllable multi-state SET memristor tuning. We present the theoretical basis of operation, the main advantages and weaknesses. We finally propose an improved closed-loop VD SET scheme to tackle the variability effect and achieve <1% tuning precision, on average 3× faster than another accurate tuning algorithm of the recent literature.Peer Reviewe

Memristor-based design solutions for mitigating parametric variations in IoT applications

PhD ThesisRapid advancement of the internet of things (IoT) is predicated by two important factors of the electronic technology, namely device size and energy-efficiency. With smaller size comes the problem of process, voltage and temperature (PVT) variations of delays which are the key operational parameters of devices. Parametric variability is also an obstacle on the way to allowing devices to work in systems with unpredictable power sources, such as those powered by energy-harvesters. Designers tackle these problems holistically by developing new techniques such as asynchronous logic, where mechanisms such as matching delays are widely used to adapt to delay variations. To mitigate energy efficiency and power interruption issues the matching delays need to be ideally retained in a non-volatile storage. Meanwhile, a resistive memory called memristor becomes a promising component for power-restricted applications owing to its inherent non-volatility. While providing non-volatility, the use of memristor in delay matching incurs some power overheads. This creates the first challenge on the way of introducing memristors into IoT devices for the delay matching. Another important factor affecting the use of memristors in IoT devices is the dependence of the memristor value on temperature. For example, a memristance decoder used in the memristor-based components must be able to correct the read data without incurring significant overheads on the overall system. This creates the second challenge for overcoming the temperature effect in memristance decoding process. In this research, we propose methods for improving PVT tolerance and energy characteristics of IoT devices from the perspective of above two main challenges: (i) utilising memristor to enhance the energy efficiency of the delay element (DE), and (ii) improving the temperature awareness and energy robustness of the memristance decoder. For memristor-based delay element (MemDE), we applied a memristor between two inverters to vary the path resistance, which determines the RC delay. This allows power saving due to the low number of switching components and the absence of external delay storage. We also investigate a solution for avoiding the unintended tuning (UT) and a timing model to estimate the proper pulse width for memristance tuning. The simulation results based on UMC 180nm technology and VTEAM model show the MemDE can provide the delay between 0.55ns and 1.44ns which is compatible to the 4-bit multiplexerbased delay element (MuxDE) in the same technology while consuming thirteen times less power. The key contribution within (i) is the development of low-power MemDE to mitigate the timing mismatch caused by PVT variations. To estimate the temperature effect on memristance, we develop an empirical temperature model which fits both titanium dioxide and silver chalcogenide memristors. The temperature experiments are conducted using the latter device, and the results confirm the validity of the proposed model with the accuracy R-squared >88%. The memristance decoder is designed to deliver two key advantages. Firstly, the temperature model is integrated into the VTEAM model to enable the temperature compensation. Secondly, it supports resolution scalability to match the energy budget. The simulation results of the 2-bit decoder based on UMC 65nm technology show the energy can be varied between 49fJ and 98fJ. This is the second major contribution to address the challenge (ii). This thesis gives future research directions into an in-depth study of the memristive electronics as a variation-robust energy-efficient design paradigm and its impact on developing future IoT applications.sponsored by the Royal Thai Governmen