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3 research outputs found

Estimating worst-case latency of on-chip interconnects with formal simulation

Author: Verbeek F.
Vugt N. van
Publication venue: 'Institute of Electrical and Electronics Engineers (IEEE)'
Publication date: 01/01/2017
Field of study

Item does not contain fulltextFMCAD :17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017) TU Wien, Vienna, Austria, October 2-6, 201

Open University of the Netherlands Research Portal

Radboud Repository

Estimating worst-case latency of on-chip interconnects with formal simulation

Author: Stewart Daryl
van Vugt - Hage Nikè
Verbeek Freek
Weissenbacher Georg
Publication venue: 'Institute of Electrical and Electronics Engineers (IEEE)'
Publication date: 01/01/2017
Field of study

Estimating worst-case latency of on-chip interconnects with formal simulation

Author: Stewart Daryl
van Vugt - Hage Nikè
Verbeek Freek
Weissenbacher Georg
Publication venue: 'Institute of Electrical and Electronics Engineers (IEEE)'
Publication date: 01/01/2017
Field of study

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