IC design for reliability

textAs the feature size of integrated circuits goes down to the nanometer scale, transient and permanent reliability issues are becoming a significant concern for circuit designers. Traditionally, the reliability issues were mostly handled at the device level as a device engineering problem. However, the increasing severity of reliability challenges and higher error rates due to transient upsets favor higher-level design for reliability (DFR). In this work, we develop several methods for DFR at the circuit level. A major source of transient errors is the single event upset (SEU). SEUs are caused by high-energy particles present in the cosmic rays or emitted by radioactive contaminants in the chip packaging materials. When these particles hit a N+/P+ depletion region of an MOS transistor, they may generate a temporary logic fault. Depending on where the MOS transistor is located and what state the circuit is at, an SEU may result in a circuit-level error. We analyze SEUs both in combinational logic and memories (SRAM). For combinational logic circuit, we propose FASER, a Fast Analysis tool of Soft ERror susceptibility for cell-based designs. The efficiency of FASER is achieved through its static and vector-less nature. In order to evaluate the impact of SEU on SRAM, a theory for estimating dynamic noise margins is developed analytically. The results allow predicting the transient error susceptibility of an SRAM cell using a closedform expression. Among the many permanent failure mechanisms that include time-dependent oxide breakdown (TDDB), electro-migration (EM), hot carrier effect (HCE), and negative bias temperature instability (NBTI), NBTI has recently become important. Therefore, the main focus of our work is NBTI. NBTI occurs when the gate of PMOS is negatively biased. The voltage stress across the gate generates interface traps, which degrade the threshold voltage of PMOS. The degraded PMOS may eventually fail to meet timing requirement and cause functional errors. NBTI becomes severe at elevated temperatures. In this dissertation, we propose a NBTI degradation model that takes into account the temperature variation on the chip and gives the accurate estimation of the degraded threshold voltage. In order to account for the degradation of devices, traditional design methods add guard-bands to ensure that the circuit will function properly during its lifetime. However, the worst-case based guard-bands lead to significant penalty in performance. In this dissertation, we propose an effective macromodel-based reliability tracking and management framework, based on a hybrid network of on-chip sensors, consisting of temperature sensors and ring oscillators. The model is concerned specifically with NBTIinduced transistor aging. The key feature of our work, in contrast to the traditional tracking techniques that rely solely on direct measurement of the increase of threshold voltage or circuit delay, is an explicit macromodel which maps operating temperature to circuit degradation (the increase of circuit delay). The macromodel allows for costeffective tracking of reliability using temperature sensors and is also essential for enabling the control loop of the reliability management system. The developed methods improve the over-conservatism of the device-level, worstcase reliability estimation techniques. As the severity of reliability challenges continue to grow with technology scaling, it will become more important for circuit designers/CAD tools to be equipped with the developed methods.Electrical and Computer Engineerin

Control and analysis of a unified power flow controller

This paper presents a control scheme and comprehensive analysis for a unified power flow controller (UPFC) on the basis of theory, computer simulation and experiment. This developed theoretical analysis reveals that a conventional power feedback control scheme makes the UPFC induce power fluctuation in transient states. The conventional control scheme cannot attenuate the power fluctuation, and so the time constant of damping is independent of active and reactive power feedback gains integrated in its control circuit. This paper proposes an advanced control scheme which has the function of successfully damping out the power fluctuation. A UPFC rated at 10 kVA is designed and constructed, which is a combination of a series device consisting of three single-phase pulsewidth modulation (PWM) converters and a shunt device consisting of a three-phase diode rectifier. Although the dynamics of the shunt device are not included, it is possible to confirm and demonstrate the performance of the series device. Experimental results agree well with both analytical and simulated results and show viability and effectiveness of the proposed control scheme </p

Fault-tolerant sub-lithographic design with rollback recovery

Shrinking feature sizes and energy levels coupled with high clock rates and decreasing node capacitance lead us into a regime where transient errors in logic cannot be ignored. Consequently, several recent studies have focused on feed-forward spatial redundancy techniques to combat these high transient fault rates. To complement these studies, we analyze fine-grained rollback techniques and show that they can offer lower spatial redundancy factors with no significant impact on system performance for fault rates up to one fault per device per ten million cycles of operation (Pf = 10^-7) in systems with 10^12 susceptible devices. Further, we concretely demonstrate these claims on nanowire-based programmable logic arrays. Despite expensive rollback buffers and general-purpose, conservative analysis, we show the area overhead factor of our technique is roughly an order of magnitude lower than a gate level feed-forward redundancy scheme

One-cycle control of switching converters

A new large-signal nonlinear control technique is proposed to control the duty-ratio d of a switch such that in each cycle the average value of a switched variable of the switching converter is exactly equal to or proportional to the control reference in the steady-state or in a transient. One-cycle control rejects power source perturbations in one switching cycle; the average value of the switched variable follows the dynamic reference in one switching cycle; and the controller corrects switching errors in one switching cycle. There is no steady-state error nor dynamic error between the control reference and the average value of the switched variable. Experiments with a constant frequency buck converter have demonstrated the robustness of the control method and verified the theoretical predictions. This new control method is very general and applicable to all types of pulse-width-modulated, resonant-based, or soft-switched switching converters for either voltage or current control in continuous or discontinuous conduction mode. Furthermore, it can be used to control any physical variable or abstract signal that is in the form of a switched variable or can be converted to the form of a switched variable

System configuration, fault detection, location, isolation and restoration: a review on LVDC Microgrid protections

Low voltage direct current (LVDC) distribution has gained the significant interest of research due to the advancements in power conversion technologies. However, the use of converters has given rise to several technical issues regarding their protections and controls of such devices under faulty conditions. Post-fault behaviour of converter-fed LVDC system involves both active converter control and passive circuit transient of similar time scale, which makes the protection for LVDC distribution significantly different and more challenging than low voltage AC. These protection and operational issues have handicapped the practical applications of DC distribution. This paper presents state-of-the-art protection schemes developed for DC Microgrids. With a close look at practical limitations such as the dependency on modelling accuracy, requirement on communications and so forth, a comprehensive evaluation is carried out on those system approaches in terms of system configurations， fault detection, location, isolation and restoration

Observer based feedback control of 3rd order LCC resonant converters

The paper considers specific issues related to the design and realisation of observer-based feedback of isolated output voltage for resonant power converters. To provide a focus to the study, a 3rd order LCC converter is employed as a candidate topology. It is shown that whilst resonant converters nominally operate at high switching frequencies to facilitate the use of small reactive components, by appropriate pre-conditioning of non-isolated resonant-tank voltages and currents, the resulting observer can be implemented at relatively low sampling frequencies, and hence, take advantage of low-cost digital hardware. Experimental results are used to demonstrate the accuracy of observer estimates under both transient and steady-state operating conditions, and to show operation of the observer as part of a closed-loop feedback system where the LCC resonant converter is used as a regulated power supply

Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design

New nanotechnology based devices are replacing CMOS devices to overcome CMOS technology's scaling limitations. However, many such devices exhibit non-monotonic I-V characteristics and uncertain properties which lead to the negative differential resistance (NDR) problem and the chaotic performance. This paper proposes a new circuit simulation approach that can effectively simulate nanotechnology devices with uncertain input sources and negative differential resistance (NDR) problem. The experimental results show a 20-30 times speedup comparing with existing simulators.Comment: Submitted on behalf of EDAA (http://www.edaa.com/