13 research outputs found

    Proof Generation for CDCL Solvers Using Gauss-Jordan Elimination

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    Traditional Boolean satisfiability (SAT) solvers based on the conflict-driven clause-learning (CDCL) framework fare poorly on formulas involving large numbers of parity constraints. The CryptoMiniSat solver augments CDCL with Gauss-Jordan elimination to greatly improve performance on these formulas. Integrating the TBUDDY proof-generating BDD library into CryptoMiniSat enables it to generate unsatisfiability proofs when using Gauss-Jordan elimination. These proofs are compatible with standard, clausal proof frameworks.Comment: Presented at 2022 Workshop on the Pragmatics of SA

    Generating Extended Resolution Proofs with a BDD-Based SAT Solver

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    In 2006, Biere, Jussila, and Sinz made the key observation that the underlying logic behind algorithms for constructing Reduced, Ordered Binary Decision Diagrams (BDDs) can be encoded as steps in a proof in the extended resolution logical framework. Through this, a BDD-based Boolean satisfiability (SAT) solver can generate a checkable proof of unsatisfiability for a set of clauses. Such a proof indicates that the formula is truly unsatisfiable without requiring the user to trust the BDD package or the SAT solver built on top of it. We extend their work to enable arbitrary existential quantification of the formula variables, a critical capability for BDD-based SAT solvers. We demonstrate the utility of this approach by applying a prototype solver to several problems that are very challenging for search-based SAT solvers, obtaining polynomially sized proofs on benchmarks for parity formulas, as well as the Urquhart, mutilated chessboard, and pigeonhole problems.Comment: Extended version of paper published at TACAS 202

    Equivalent Literal Propagation in the DLL Procedure

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    We propose a simple data structure to represent all equivalent literals such as l 1 $ l 2 in a CNF formula F , and implement a special look-ahead technique, called equivalency reasoning, to propagate these equivalent literals in F in order to get other equivalent literals and to simplify F . Equivalent literal propagation remedies the ineffectiveness of unit propagation on equivalent literals and makes easy many SAT problems containing both usual CNF clauses and the so-called equivalency clauses (Ex-OR or modulo 2 arithmetics). Our approach is also compared with general CSP look-back techniques on these problems

    Tools and Algorithms for the Construction and Analysis of Systems

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    This open access book constitutes the proceedings of the 28th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, TACAS 2022, which was held during April 2-7, 2022, in Munich, Germany, as part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2022. The 46 full papers and 4 short papers presented in this volume were carefully reviewed and selected from 159 submissions. The proceedings also contain 16 tool papers of the affiliated competition SV-Comp and 1 paper consisting of the competition report. TACAS is a forum for researchers, developers, and users interested in rigorously based tools and algorithms for the construction and analysis of systems. The conference aims to bridge the gaps between different communities with this common interest and to support them in their quest to improve the utility, reliability, exibility, and efficiency of tools and algorithms for building computer-controlled systems

    Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022

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    The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing
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