Novel CMOS RFIC Layout Generation with Concurrent Device Placement and Fixed-Length Microstrip Routing

With advancing process technologies and booming IoT markets, millimeter-wave CMOS RFICs have been widely developed in re- cent years. Since the performance of CMOS RFICs is very sensi- tive to the precision of the layout, precise placement of devices and precisely matched microstrip lengths to given values have been a labor-intensive and time-consuming task, and thus become a major bottleneck for time to market. This paper introduces a progressive integer-linear-programming-based method to gener- ate high-quality RFIC layouts satisfying very stringent routing requirements of microstrip lines, including spacing/non-crossing rules, precise length, and bend number minimization, within a given layout area. The resulting RFIC layouts excel in both per- formance and area with much fewer bends compared with the simulation-tuning based manual layout, while the layout gener- ation time is significantly reduced from weeks to half an hour.Comment: ACM/IEEE Design Automation Conference (DAC), 201

A Novel Space-Time-Speed Method for Increasing the Passing Capacity with Safety Guaranteed of Railway Station

A method for improving the passing capacity of a station without adding any track and equipment is proposed in this paper. In the process of handling train routes, by transforming the existing fixed train-approaching locking section into a variable mode, the route locking time is shortened and in-station resource consumption is reduced. This approach improves the capacity of the station. At the same time, delay of the train can be quickly returned to normal. A method of variable train-approaching locking section is discussed; a mathematical model for increasing station passing capacity is shown. Comparison between the impact of a variable train-approaching locking section and a fixed mode on the station passing capacity is shown

Vlsi Implementation of Olfactory Cortex Model

This thesis attempts to implement the building blocks required for the realization of the biologically motivated olfactory neural model in silicon as the special purpose hardware. The olfactory model is originally developed by R. Granger, G. Lynch, and Ambros-Ingerson. CMOS analog integrated circuits were used for this purpose. All of the building blocks were fabricated using the MOSIS service and tested at our site. The results of this study can be used to realize a system level integration of the olfactory model.Electrical Engineerin

Techniques de routage pseudo-aléatoire pour une application micro-électronique

Résumé La problématique de routage est très actuelle. On en trouve des applications dans les GPS, les prévisions de trafic routier, mais aussi pour le prototypage sur FPGA, la fabrication de puces électroniques ou le trafic TCP/IP sur Internet. On trouve des publications sur le sujet depuis plusieurs dizaines d'années, mais on observe actuellement une recrudescence confirmant l'actualité, l'importance et la complexité de ce problème. Cette thèse concerne le routage et ses ressources pour une application dans un nouveau type de système micro-électronique, nommé le WaferBoardTM . Son noyau consiste en un circuit électronique intégré à l'échelle d'une tranche de silicium (wafer). Peu d'applications commerciales de la micro-électronique ont exploité ce niveau d'intégration. Ce système de prototypage rapide vise à réduire d'un ou deux ordres de grandeur le temps de développement de systèmes électroniques. Il nécessite un ensemble d'outils logiciel de support, dont un outil de routage très rapide, capable de produire des solutions valables en des temps de l'ordre de la minute, et de certaines fonctionnalités spécifiques, l'équilibrage de délai ou le reroutage à la volée, au sein d'une netlist déjà routée. La problématique de routage pour cette application peut être imagée comme suit. Étant donné un réseau routier régulier (les routes d’Amériques du Nord en version cartésienne par exemple) et 100,000 voitures au départ lundi à 8h a.m. dans tout le pays avec des sources et destinations très variées; calculer les chemins pour toutes les voitures de telle sorte qu'aucune ne prenne la même route dans la journée. Il est 7h59 a.m, vous avez 1 minute, et des ponts sont inaccessibles pour travaux, en voici la liste. Cet exemple simpliste donne une idée des ordres de grandeurs de la problématique de routage que l'on cherche à résoudre pour cette application. Un algorithme de routage prend en paramètres deux structures de données : un graphe (ou réseau d'interconnexions) constitué de n\oe{}uds (sommets) et d'arcsUn arc relie deux sommets du graphe, et une netlistDans ce contexte, un netlist réfère à une liste d'interconnexions entre composants, liste de n\oe{}uds électriques dont les points de départ et d'arrivée sont positionnés géographiquement. Ainsi, au lieu de voitures, il s'agit de router des signaux électriques dont les points de départ et d'arrivée sont dictés par la position des broches des composants placés sur le système de prototypage. Un réseau régulier maillé mufti-dimensionnel (plus généralement appelé « réseau d'interconnexions ») sert de réseau routier dont certaines routes sont défectueuses, des ponts inaccessibles. En effet, le réseau d'interconnexions est un circuit électronique intégré à l'échelle d'une tranche de silicium complète, ce qui implique la présence de défectuosités au sein de chaque circuit fabriqué. Contrairement aux circuits électroniques classiques, où chacun est testé et les défectueux écartés, une intégration à l'échelle de la tranche demande de fortes redondances au sein du circuit pour minimiser le taux de rejets. Pour l'application du WaferBoard, un certain nombre d'éléments du réseau d'interconnexions seront fort probablement défectueux sur chaque circuit produit; l'algorithme de routage se doit de prendre en compte ces éléments très particuliers. Cette contrainte ne se retrouve pas dans les applications plus classiques des routeurs que l'on retrouve dans les PCB, circuits FPGA ou circuits VLSI. D'autres contraintes s'appliquent à ce projet particulier : la latence induite par la technologie est environ un ordre de grandeur plus importante que celle dans les circuits sur PCB, ce qui impose un routage orienté vers sa réduction.----------Abstract The routing problem is very actual. Applications are found in GPS, road traffic forecast, but also for prototyping on FPGA, or TCP/IP traffic on the Internet. Publications on the subject have existed for several decades, but new publications keep appearing, confirming the importance and complexity of the problem. This thesis deals with routing and the resources it requires for a new category of micro-electronic applications, called the WaferBoard. It is an electronic circuit integrated at the wafer scale. Few commercial applications of micro-electronics have exploited this level of integration. This rapid prototyping system aims at reducing by one or two orders of magnitude the development time of digital circuits. It requires a very fast routing tool, capable of producing viable solutions in a few minutes, with dedicated functionality such as balancing delays and rerouting on the fly parts of a netlist. The routing problem for this application can be pictured as follows. Given a regular road network of the size of north america, if 100.000 cars were to start Monday 8 a.m. across the continent with a wide variety of sources and destinations; the challenge is to compute paths for all cars so none of them take the same route that day. It is 7:59 am, you have 1 minute, and some bridges are under road work: here is the list. This simplistic example gives an idea of the orders of magnitude of the problem that need to be solved for this application. A routing algorithm takes as input: a graph (or interconnection network) made of nodes and edges, and a netlst, a list of electrical nodes with starting and ending points physically placed. Therefore, instead of cars, the problem consists of routing electrical signals with points of departure and arrival dictated by the pin position of components placed on the prototyping system. A regular, multi-dimensional mesh (also called "interconnection network") serves as a road network, which contains defective roads and inaccessible bridges. Indeed, the interconnection network is an electronic circuit integrated across a full wafer, implying the presence of defects within each manufactured circuit. Unlike conventional electronic circuits, where each is tested and defective ones are set apart, wafer scale integrated applications require lots of redundancy in the circuit to minimize the rejection rate. In the WaferBoard, a number of elements of the interconnection network will be defective in each circuit; the routing algorithm must take into account these very specific elements. This constraint is not found in the classic applications of routers found in PCB, FPGA or VLSI circuits. Other restrictions apply to this particular project: the latency induced by the technology is about one order of magnitude greater than that in the circuits of PCBs, which requires a routing oriented towards computation time reduction. This constraint partly explains the network architecture used. Within the WaferIC, the shortest distance is not necessarily the one that offers the smallest latency. This property of the network complexifies the routing problem. Balancing delays within a group of arbitrary size nets is a necessary feature of the routing algorithm, and the difficulty is amplified by the computation time limit. Indeed, the interest of the application is to reduce the time for a user to test a circuit: the time of setup is extremely short, and estimated at a few minutes only

Enabling Technologies for 3D ICs: TSV Modeling and Analysis

Through silicon via (TSV) based three-dimensional (3D) integrated circuit (IC) aims to stack and interconnect dies or wafers vertically. This emerging technology offers a promising near-term solution for further miniaturization and the performance improvement of electronic systems and follows a more than Moore strategy. Along with the need for low-cost and high-yield process technology, the successful application of TSV technology requires further optimization of the TSV electrical modeling and design. In the millimeter wave (mmW) frequency range, the root mean square (rms) height of the TSV sidewall roughness is comparable to the skin depth and hence becomes a critical factor for TSV modeling and analysis. The impact of TSV sidewall roughness on electrical performance, such as the loss and impedance alteration in the mmW frequency range, is examined and analyzed following the second order small perturbation method. Then, an accurate and efficient electrical model for TSVs has been proposed considering the TSV sidewall roughness effect, the skin effect, and the metal oxide semiconductor (MOS) effect. However, the emerging application of 3D integration involves an advanced bio-inspired computing system which is currently experiencing an explosion of interest. In neuromorphic computing, the high density membrane capacitor plays a key role in the synaptic signaling process, especially in a spike firing analog implementation of neurons. We proposed a novel 3D neuromorphic design architecture in which the redundant and dummy TSVs are reconfigured as membrane capacitors. This modification has been achieved by taking advantage of the metal insulator semiconductor (MIS) structure along the sidewall, strategically engineering the fixed oxide charges in depletion region surrounding the TSVs, and the addition of oxide layer around the bump without changing any process technology. Without increasing the circuit area, these reconfiguration of TSVs can result in substantial power consumption reduction and a significant boost to chip performance and efficiency. Also, depending on the availability of the TSVs, we proposed a novel CAD framework for TSV assignments based on the force-directed optimization and linear perturbation

Large bichromatic point sets admit empty monochromatic 4-gons

We consider a variation of a problem stated by Erd˝os and Szekeres in 1935 about the existence of a number fES(k) such that any set S of at least fES(k) points in general position in the plane has a subset of k points that are the vertices of a convex k-gon. In our setting the points of S are colored, and we say that a (not necessarily convex) spanned polygon is monochromatic if all its vertices have the same color. Moreover, a polygon is called empty if it does not contain any points of S in its interior. We show that any bichromatic set of n ≥ 5044 points in R2 in general position determines at least one empty, monochromatic quadrilateral (and thus linearly many).Postprint (published version