Enhancing Physical Layer Security in AF Relay Assisted Multi-Carrier Wireless Transmission

In this paper, we study the physical layer security (PLS) problem in the dual hop orthogonal frequency division multiplexing (OFDM) based wireless communication system. First, we consider a single user single relay system and study a joint power optimization problem at the source and relay subject to individual power constraint at the two nodes. The aim is to maximize the end to end secrecy rate with optimal power allocation over different sub-carriers. Later, we consider a more general multi-user multi-relay scenario. Under high SNR approximation for end to end secrecy rate, an optimization problem is formulated to jointly optimize power allocation at the BS, the relay selection, sub-carrier assignment to users and the power loading at each of the relaying node. The target is to maximize the overall security of the system subject to independent power budget limits at each transmitting node and the OFDMA based exclusive sub-carrier allocation constraints. A joint optimization solution is obtained through duality theory. Dual decomposition allows to exploit convex optimization techniques to find the power loading at the source and relay nodes. Further, an optimization for power loading at relaying nodes along with relay selection and sub carrier assignment for the fixed power allocation at the BS is also studied. Lastly, a sub-optimal scheme that explores joint power allocation at all transmitting nodes for the fixed subcarrier allocation and relay assignment is investigated. Finally, simulation results are presented to validate the performance of the proposed schemes.Comment: 10 pages, 7 figures, accepted in Transactions on Emerging Telecommunications Technologies (ETT), formerly known as European Transactions on Telecommunications (ETT

Secrecy Rate Analysis of UAV-Enabled mmWave Networks Using Matern Hardcore Point Processes

Communications aided by low-altitude unmanned aerial vehicles (UAVs) have emerged as an effective solution to provide large coverage and dynamic capacity for both military and civilian applications, especially in unexpected scenarios. However, because of their broad coverage, UAV communications are prone to passive eavesdropping attacks. This paper analyzes the secrecy performance of UAVs networks at the millimeter wave band and takes into account unique features of air-to-ground channels and practical constraints of UAV deployment. To be specific, it explores the 3-D antenna gain in the air-to-ground links and uses the Matérn hardcore point process to guarantee the safety distance between the randomly deployed UAV base stations. In addition, we propose the transmit jamming strategy to improve the secrecy performance in which part of UAVs send jamming signals to confound the eavesdroppers. Simulation results verify our analysis and demonstrate the impact of different system parameters on the achievable secrecy rate. It is also revealed that optimizing the density of jamming UAVs will significantly improve security of UAV-enabled networks

GHz Range CMOS LNA

This thesis work presents 7GHz CMOS Common Gate LNA, Layout design and a scaled down version of the same topology with BJT, operating frequency of 5MHz. Schematic was designed in OrCAD Capture CIS, gain and linearity results were taken. PCB LNA was modified to operate at the target frequency of 5MHz. Its linearity, gain measurements and practical results were taken by using oscilloscope and spectrum analyzers. These measurements results were then compared with the results taken previously in OrCAD Capture CIS design environment. Both the measurement results were taken by giving different input powers. The goal was to check the behavior of LNA and to see the effects of different components on its gain and linearity. Also the task was to find out for what range of input power it remains linear and stable. Another part of this thesis work is GHz range Complementary Metal Oxide Semiconductor (CMOS) LNA and then followed by the design layout for the circuit. Schematic for GHz range LNA was designed using Cadence Virtuoso 45nm technology, and operational frequency target was 7GHz. The design followed mainly the same methodology as it was for the MHz range LNA, but here in CMOS technology the higher operational frequency was selected. Common gate stage was designed to operate at targeted frequency, and since common gate has low input and high output impedance, buffer stage is needed for output matching. White’s Cascode buffer stage was introduced for output impedance matching. Different parameters results are needed to be achieved for LNA design before stepping forward into Layout design. Such as Scattering parameters, Noise Figure, Stability, transient analysis, Linearity, 1dB compression point and IP3 measurement. Next part of thesis work consists of Layout design of 7GHz CMOS LNA. A Layout was carefully designed by taking care of allocation of metal layers to avoid extra sheet resistances, and paths were capable of withstanding enough current density. Its parasitic extracted results were compared with the results obtained from the schematic design. Clear difference was noticed during comparison between important parameters, such as gain and operational frequency