동기 회로에서 시간 오류를 고려한 공급전압 제어

학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 2. 최기영.Modern embedded systems are becoming more and more constrained by power consumption. While we require those systems to compute even more data at faster speed, lowering energy consumption is essential to preserve battery life as well as integrity of devices. Amongst many techniques to reduce power consumption of chips such as power gating, clock gating, etc., lowering the supply voltage (maybe reducing chips frequency) is known to be the most effective one. However, lowering the supply voltage of chips too much down to near the threshold voltage of transistors causes the logic delay to vary exponentially with intrinsic and extrinsic variations (process variations, temperature, aging, etc.) and thus forces the designer to set increased timing margin. This thesis proposes a technique for automatically adjusting the supply voltage to match the speed of a logic block with a given time constraint. Depending on process and temperature variations, our technique chooses the minimum supply voltage to satisfy the timing constraint defined by the designer. This allows him/her to reduce the default supply voltage of the logic block and thus save power. In our experiments at the 28/32nm technology node, we succeeded in reducing the logic block power by 52% on average by varying the supply voltage between 0.55V and 1V, while the nominal supply voltage is 1.05V.Abstract Contents List of Figures List of Tables Chapter 1 Introduction 1 Chapter 2 Background 5 1.1 Near-Threshold Computing 5 1.2 Current Sensing Completion Detection 7 Chapter 3 Proposed Approach 12 Chapter 4 Experimental setup 16 4.1 Intrinsic Variations 16 4.2 Extrinsic Variations 17 4.3 Control Block 17 4.4 Logic Block 17 4.5 Experimental parameters 19 Chapter 5 Experimental Results 20 5.1 Results at the TT 22 5.2 Result at the FF 22 5.3 Results at the SS 22 5.4 Effect on temperature 25U 5.5 Final power savings 26 Chapter 6 Conclusion and future work 29 Bibliography 31Maste

Energy-minimum sub-threshold self-timed circuits using current-sensing completion detection

This study addresses the design of self-timed energy-minimum circuits, operating in the sub-VT domain and a generic implementation template using bundled-data circuitry and current sensing completion detection (CSCD). Furthermore, a fully decoupled latch controller was developed, which integrates with the current-sensing circuitry. Different configurations that utilise the proposed latch controller are highlighted. A contemporary synchronous electronic design automation tools-based design flow, which transforms a synchronous design into a corresponding self-timed circuit, is outlined. Different use cases of the CSCD system are examined. The design flow and the current-sensing technique are validated by the implementation of a self-timed version of a wavelet-based event detector for cardiac pacemaker applications in a standard 65 nm CMOS process. The chip was fabricated and verified to operate down to 250 mV. Spice simulations indicate a gain of 52.58% in throughput because of asynchronous operation. By trading the throughput improvement, energy dissipation is reduced by 16.8% at the energy-minimum supply voltage