Energy-Efficient Antenna Selection and Power Allocation for Large-Scale Multiple Antenna Systems with Hybrid Energy Supply

The combination of energy harvesting and large-scale multiple antenna technologies provides a promising solution for improving the energy efficiency (EE) by exploiting renewable energy sources and reducing the transmission power per user and per antenna. However, the introduction of energy harvesting capabilities into large-scale multiple antenna systems poses many new challenges for energy-efficient system design due to the intermittent characteristics of renewable energy sources and limited battery capacity. Furthermore, the total manufacture cost and the sum power of a large number of radio frequency (RF) chains can not be ignored, and it would be impractical to use all the antennas for transmission. In this paper, we propose an energy-efficient antenna selection and power allocation algorithm to maximize the EE subject to the constraint of user's quality of service (QoS). An iterative offline optimization algorithm is proposed to solve the non-convex EE optimization problem by exploiting the properties of nonlinear fractional programming. The relationships among maximum EE, selected antenna number, battery capacity, and EE-SE tradeoff are analyzed and verified through computer simulations.Comment: IEEE Globecom 2014 Selected Areas in Communications Symposium-Green Communications and Computing Trac

Green HPC: Optimizing Software Stack Energy Efficiency of Large Data Systems

High-performance computing (HPC) is indispensable in modern scientific research and industry applications, but its energy consumption is a growing concern. This thesis presents two novel approaches to optimize energy consumption in large data systems. The first chapter of the thesis will discuss the use of Dynamic Voltage and Frequency Scaling (DVFS) to optimize the energy efficiency of two popular lossy compression algorithms: SZ and ZFP. By adjusting the voltage and frequency levels of computing resources, DVFS can reduce energy consumption while maintaining the desired level of performance and accuracy. The second chapter of the thesis will focus on a detailed comparison and analysis of asynchronous and synchronous checkpointing energy consumption using the VELOC and GenericIO libraries. The study investigates the trade-offs between these two checkpointing techniques, offering insights into their energy consumption patterns and performance impacts on large-scale HPC systems. Based on the analysis, we provide recommendations for choosing the most energy-efficient checkpointing method for specific application scenarios. Together, these two approaches contribute to the development of Green HPC, paving the way for more sustainable and energy-efficient large data systems. This thesis will provide valuable insights for researchers and industry practitioners aiming to optimize energy consumption while maintaining high-performance computing capabilities. i

Doctor of Philosophy

dissertationThe computing landscape is undergoing a major change, primarily enabled by ubiquitous wireless networks and the rapid increase in the use of mobile devices which access a web-based information infrastructure. It is expected that most intensive computing may either happen in servers housed in large datacenters (warehouse- scale computers), e.g., cloud computing and other web services, or in many-core high-performance computing (HPC) platforms in scientific labs. It is clear that the primary challenge to scaling such computing systems into the exascale realm is the efficient supply of large amounts of data to hundreds or thousands of compute cores, i.e., building an efficient memory system. Main memory systems are at an inflection point, due to the convergence of several major application and technology trends. Examples include the increasing importance of energy consumption, reduced access stream locality, increasing failure rates, limited pin counts, increasing heterogeneity and complexity, and the diminished importance of cost-per-bit. In light of these trends, the memory system requires a major overhaul. The key to architecting the next generation of memory systems is a combination of the prudent incorporation of novel technologies, and a fundamental rethinking of certain conventional design decisions. In this dissertation, we study every major element of the memory system - the memory chip, the processor-memory channel, the memory access mechanism, and memory reliability, and identify the key bottlenecks to efficiency. Based on this, we propose a novel main memory system with the following innovative features: (i) overfetch-aware re-organized chips, (ii) low-cost silicon photonic memory channels, (iii) largely autonomous memory modules with a packet-based interface to the proces- sor, and (iv) a RAID-based reliability mechanism. Such a system is energy-efficient, high-performance, low-complexity, reliable, and cost-effective, making it ideally suited to meet the requirements of future large-scale computing systems

SCORE: Simulator for cloud optimization of resources andenergy consumption

Achieving efficiency both in terms of resource utilisation and energy consumption is acomplex challenge, especially in large-scale wide-purpose data centers that serve cloud- computing services. Simulation presents an appropriate solution for the development andtesting of strategies that aim to improve efficiency problems before their applications inproduction environments. Various cloud simulators have been proposed to cover differentaspects of the operation environment of cloud-computing systems. In this paper, we define the SCORE tool, which is dedicated to the simulation of energy-efficient monolithicand parallel-scheduling models and for the execution of heterogeneous, realistic and synthetic workloads. The simulator has been evaluated through empirical tests. The results ofthe experiments confirm that SCORE is a performant and reliable tool for testing energy- efficiency, security, and scheduling strategies in cloud-computing environments.European Cooperation in Science and Technology (COST) COST Action IC140

Memristive tonotopic mapping with volatile resistive switching memory devices

: To reach the energy efficiency and the computing capability of biological neural networks, novel hardware systems and paradigms are required where the information needs to be processed in both spatial and temporal domains. Resistive switching memory (RRAM) devices appear as key enablers for the implementation of large-scale neuromorphic computing systems with high energy efficiency and extended scalability. Demonstrating a full set of spatiotemporal primitives with RRAM-based circuits remains an open challenge. By taking inspiration from the neurobiological processes in the human auditory systems, we develop neuromorphic circuits for memristive tonotopic mapping via volatile RRAM devices. Based on a generalized stochastic device-level approach, we demonstrate the main features of signal processing of cochlea, namely logarithmic integration and tonotopic mapping of signals. We also show that our tonotopic classification is suitable for speech recognition. These results support memristive devices for physical processing of temporal signals, thus paving the way for energy efficient, high density neuromorphic systems