Analysis and Design of Power Gated Low-Power, High Performance Latch Dynamic Double-Tail Comparator

This paper introduces an elite, low power dynamic hook comparator making utilization of energy gating system with the end goal of diminished power. The comparator has dependably been a heart of simple to advanced converters in VLSI circuits. The lessening in power utilization of comparator eventually diminishes the power utilization in ADC squares. The proposed configuration has been recreated on Tanner EDA at 180nm TSMC and accomplished up to 15% diminishment in power and 71% lessening on kickback clamour from the traditional plans and in view of the present outcomes and investigation. A new low power, elite comparator is proposed, where the circuit of a dynamic twofold tail comparator with power gating procedure is altered for low-power and quick operation even in little supply voltages. With no troubles in circuit plan and by including couple of transistors, the positive criticism amid the recovery is reinforced, which brings about amazingly lessened defer time. Post-design re-enactment brings about a 180nm CMOS innovation gave the examination comes about successfully. It is demonstrated that in the proposed dynamic comparator both the power utilization, defer time, kickback noise is altogether decreased

Combined Time and Information Redundancy for SEU-Tolerance in Energy-Efficient Real-Time Systems

Recently the trade-off between energy consumption and fault-tolerance in real-time systems has been highlighted. These works have focused on dynamic voltage scaling (DVS) to reduce dynamic energy dissipation and on time redundancy to achieve transient-fault tolerance. While the time redundancy technique exploits the available slack time to increase the fault-tolerance by performing recovery executions, DVS exploits slack time to save energy. Therefore we believe there is a resource conflict between the time-redundancy technique and DVS. The first aim of this paper is to propose the usage of information redundancy to solve this problem. We demonstrate through analytical and experimental studies that it is possible to achieve both higher transient fault-tolerance (tolerance to single event upsets (SEU)) and less energy using a combination of information and time redundancy when compared with using time redundancy alone. The second aim of this paper is to analyze the interplay of transient-fault tolerance (SEU-tolerance) and adaptive body biasing (ABB) used to reduce static leakage energy, which has not been addressed in previous studies. We show that the same technique (i.e. the combination of time and information redundancy) is applicable to ABB-enabled systems and provides more advantages than time redundancy alone

Students’ acceptance towards kahoot application in mastering culinary terminology

Kahoot! is a game-based learning platform used to review students’ knowledge, for formative assessment and provides an opportunity not only to assess students' conceptual understanding but also to build new knowledge through further clarification during or after the game. The objective of this study is to assess the acceptability of culinary students in the use of Kahoot! application for mastery the culinary terminology. This study aimed to identify students' acceptance of learning applications, to identify students' acceptance of Kahoot! use in terms of memory as well as students' level of mastering Kahoot! in the learning process. This study is a descriptive study that used a five-point Likert scale questionnaire as an instrument. A total of 48 second year students from the Catering program were used as the study sample. The collected data were analyzed using Statistical Package for Social Science Version 23.0 for Windows (SPSS). The results show that the aspect of students' level of mastering the culinary terminology using Kahoot! application is high with a mean score of 4.55. Whereas the students’ acceptance of Kahoot! as a learning application, was also high with a mean score of 4.44. Finally, the students’ acceptance of the culinary terminology tested using Kahoot! is high with a mean score of 4.45

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2

Communication channel analysis and real time compressed sensing for high density neural recording devices

Next generation neural recording and Brain- Machine Interface (BMI) devices call for high density or distributed systems with more than 1000 recording sites. As the recording site density grows, the device generates data on the scale of several hundred megabits per second (Mbps). Transmitting such large amounts of data induces significant power consumption and heat dissipation for the implanted electronics. Facing these constraints, efficient on-chip compression techniques become essential to the reduction of implanted systems power consumption. This paper analyzes the communication channel constraints for high density neural recording devices. This paper then quantifies the improvement on communication channel using efficient on-chip compression methods. Finally, This paper describes a Compressed Sensing (CS) based system that can reduce the data rate by > 10x times while using power on the order of a few hundred nW per recording channel