Energy-aware Software

Luca Ardito has focused his PhD on studying how to identify and to reduce the energy consumption caused by software. The project concentrates on the application level, with an experimental approach to discover and modify characteristics that waste energy. We can define five research goals: RG1. Is it possible to measure the energy consumption of an application? Measuring the energy consumption of an electronic device (PC, mobile phone, etc.) is straightforward, but several applications coexist on it, possibly with very different energy needs. Usage profiles for applications are certainly important too. We will consider the most common platforms (Windows, Linux, Mac Osx). RG2. Could Energy Efficiency be considered as a software non- functional requirement? Research has increasingly focused on improving the Energy Efficiency of hardware, but the literature still lacks in quantifying accurately the energy impact of software. This research goal is strictly related to the following one. RG3. Is it possible to profile the energy consumption of a software application? An empirical experiment could assess quantitatively the energetic impact of software usage by building up common application usage scenarios and executing them independently to collect power consumption data. RG4. Is there a relationship between the way a program is written and its energy consumption? The same application, at the code level, can be written in different ways. Here the question is if the different ways have impact on energy consumption. The code should be considered at two levels: source code (programmer) and object code/byte code (compiler). RG5. Is it possible to use the energy consumption information to trigger self-adaptation? A software application could automatically modify its behaviour in order to reduce its energy consumption

Temperature, energy and performance: addressing embedded system challenges through fast cache simulation

Temperature, energy and performance are essential design considerations during the conception of modern digital systems. The work presented in this thesis focusses on three aspects that can be used to overcome these limitations. First an evaluation of the suitability of the dynamic application adaptation method is researched with the aim of using it to control the temperature of a Field Programmable Gate Array (FPGA) device. Despite the use of an extremely adaptive custom JPEG encoder, it was determined that application adaptation alone is ineffective in an FPGA for thermal management. Next, a study is performed which aims to assess which components are principally responsible for the rise in temperatures in FPGAs. It was found that the external memory interface is a significant heat-source in FPGA-based embedded systems, and that device temperature correlates with CPU cache miss rate. The third and main aspect covered in this dissertation is the speeding up of CPU cache simulation. Single pass cache simulation is a tool that can be employed at design time to select a cache yielding acceptable temperature, system performance and energy consumption. Three Multiple cAche Simulators in Hardware (MASH) or in Software (MASS) are proposed for three cache replacement policies: MASH{lru} for the Least Recently Used (LRU) cache algorithm, MASH{fifo} for First In First Out (FIFO) and MASS{plrut} for Pseudo Least Recently Used tree (PLRUt). The former two are novel in that they are implemented in hardware and are respectively 53x and 11.10x faster than software counterparts. The PLRUt simulator presents for the first time an optimised hash table-based algorithm yielding a speedup of 1.93x over an unoptimised solution. All cache simulators employ cache properties specific to their replacement policies to improve simulator characteristics. Additionally, it is shown that the hardware (or MASH) simulators can be implemented in-system alongside an embedded system, allowing for the direct trace extraction and cache simulation from within an FPGA. Using in-system simulation, large speedups can be achieved as trace generation and multiple cache simulation happen at the same time at high frequencies