2,202 research outputs found
Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines
Large-capacity Content Addressable Memory (CAM) is a key element in a wide
variety of applications. The inevitable complexities of scaling MOS transistors
introduce a major challenge in the realization of such systems. Convergence of
disparate technologies, which are compatible with CMOS processing, may allow
extension of Moore's Law for a few more years. This paper provides a new
approach towards the design and modeling of Memristor (Memory resistor) based
Content Addressable Memory (MCAM) using a combination of memristor MOS devices
to form the core of a memory/compare logic cell that forms the building block
of the CAM architecture. The non-volatile characteristic and the nanoscale
geometry together with compatibility of the memristor with CMOS processing
technology increases the packing density, provides for new approaches towards
power management through disabling CAM blocks without loss of stored data,
reduces power dissipation, and has scope for speed improvement as the
technology matures.Comment: 10 pages, 11 figure
Design of Adiabatic MTJ-CMOS Hybrid Circuits
Low-power designs are a necessity with the increasing demand of portable
devices which are battery operated. In many of such devices the operational
speed is not as important as battery life. Logic-in-memory structures using
nano-devices and adiabatic designs are two methods to reduce the static and
dynamic power consumption respectively. Magnetic tunnel junction (MTJ) is an
emerging technology which has many advantages when used in logic-in-memory
structures in conjunction with CMOS. In this paper, we introduce a novel
adiabatic hybrid MTJ/CMOS structure which is used to design AND/NAND, XOR/XNOR
and 1-bit full adder circuits. We simulate the designs using HSPICE with 32nm
CMOS technology and compared it with a non-adiabatic hybrid MTJ/CMOS circuits.
The proposed adiabatic MTJ/CMOS full adder design has more than 7 times lower
power consumtion compared to the previous MTJ/CMOS full adder
Design considerations of a nonvolatile accumulator-based 8-bit processor
The rise of the Internet of Things (IoT) and theconstant growth of portable electronics have leveraged the con-cern with energy consumption. Nonvolatile memory (NVM)emerged as a solution to mitigate the problem due to its abilityto retain data on sleep mode without a power supply. Non-volatile processors (NVPs) may further improve energy savingby using nonvolatile flip-flops (NVFFs) to store system state,allowing the device to be turned off when idle and resume ex-ecution instantly after power-on. In view of the potential pre-sented by NVPs, this work describes the initial steps to imple-ment a nonvolatile version of Neander, a hypothetical processorcreated for educational purposes. First, we implemented Ne-ander in Register Transfer Level (RTL), separating the com-binational logic from the sequential elements. Then, the lat-ter was replaced by circuit-level descriptions of volatile flip-flops. We then validated this implementation by employinga mixed-signal simulation over a set of benchmarks. Resultshave shown the expected behavior for the whole instructionset. Then, we implemented circuit-level descriptions of mag-netic tunnel junction (MTJ) based nonvolatile flip-flops, usingan open-source MTJ model. These elements were exhaustivelyvalidated using electrical simulations. With these results, weintend to carry on the implementation and fully equip our pro-cessor with nonvolatile features such as instant wake-up
Cryogenic Memory Technologies
The surging interest in quantum computing, space electronics, and
superconducting circuits has led to new developments in cryogenic data storage
technology. Quantum computers promise to far extend our processing capabilities
and may allow solving currently intractable computational challenges. Even with
the advent of the quantum computing era, ultra-fast and energy-efficient
classical computing systems are still in high demand. One of the classical
platforms that can achieve this dream combination is superconducting single
flux quantum (SFQ) electronics. A major roadblock towards implementing scalable
quantum computers and practical SFQ circuits is the lack of suitable and
compatible cryogenic memory that can operate at 4 Kelvin (or lower)
temperature. Cryogenic memory is also critically important in space-based
applications. A multitude of device technologies have already been explored to
find suitable candidates for cryogenic data storage. Here, we review the
existing and emerging variants of cryogenic memory technologies. To ensure an
organized discussion, we categorize the family of cryogenic memory platforms
into three types: superconducting, non-superconducting, and hybrid. We
scrutinize the challenges associated with these technologies and discuss their
future prospects.Comment: 21 pages, 6 figures, 1 tabl
A Study on Performance and Power Efficiency of Dense Non-Volatile Caches in Multi-Core Systems
In this paper, we present a novel cache design based on Multi-Level Cell
Spin-Transfer Torque RAM (MLC STTRAM) that can dynamically adapt the set
capacity and associativity to use efficiently the full potential of MLC STTRAM.
We exploit the asymmetric nature of the MLC storage scheme to build cache lines
featuring heterogeneous performances, that is, half of the cache lines are
read-friendly, while the other is write-friendly. Furthermore, we propose to
opportunistically deactivate ways in underutilized sets to convert MLC to
Single-Level Cell (SLC) mode, which features overall better performance and
lifetime. Our ultimate goal is to build a cache architecture that combines the
capacity advantages of MLC and performance/energy advantages of SLC. Our
experiments show an improvement of 43% in total numbers of conflict misses, 27%
in memory access latency, 12% in system performance, and 26% in LLC access
energy, with a slight degradation in cache lifetime (about 7%) compared to an
SLC cache
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