Hash Based Four Level Image Cryptography

he paper presents a four level image encryption cryptography based on hash i.e. a replacing table for giving new values to the pixels. The basic motive of this work is to provide a technique for securing the images to the level that one is not able to recognize it while transmission to prevent the attack of intruders. In this paper multi level image cryptography is used base d on chaotic system which employs random integer function for the diffusion phase. The proposed algorithm provides large key space. Results are compared in terms of correlation coefficient which satisfies the property of zero correlation. In this paper it is proposed that multi level image cryptography to securely encrypt the images for the purpose of storing images and transmitting them ov er the Internet. There are two major advantages associated with this system. The first advantage is that it makes the encrypted im age with a constant increasing intensity. The second advantage is that it does not impose any restriction on the decoding of the specifi c image signal because with every new image signal it produces a new hash accordingly. Our system would be systematically evaluated, and it shows a high level of security with excellent image quality

VLSI implementation of AES algorithm

In the present era of information processing through computers and access of private information over the internet like bank account information even the transaction of money, business deal through video conferencing, encryption of the messages in various forms has become inevitable. There are mainly two types of encryption algorithms, private key (also called symmetric key having single key for encryption and decryption) and public key (separate key for encryption and decryption). In the present work, hardware optimization for AES architecture has been done in different stages. The hardware comparison results show that as AES architecture has critical path delay of 9.78 ns when conventional s-box is used, whereas it has critical path delay of 8.17 ns using proposed s-box architecture. The total clock cycles required to encrypt 128 bits of data using proposed AES architecture are 86 and therefore, throughput of the AES design in Spartan-6 of Xilinx FPGA is approximately 182.2 Mbits/s. To achieve the very high speed, full custom design of s-box in composite field has been done for the proposed s-box architecture in Cadence Virtuoso. The novel XOR gate is proposed for use in s-box design which is efficient in terms of delay and power along with high noise margin. The implementation has been done in 180 nm UMC technology. Total dynamic power in the proposed XOR gate is 0.63 µW as compared to 5.27 µW in the existing design of XOR. The designed s-box using proposed XOR occupies a total area of 27348 µm2. The s-box chip consumes 22.6 µW dynamic power and has 8.2 ns delay after post layout simulation has been performed