Проєктування та самодіагностика кіберфізичних пристроїв керування на платформі SoC

The subject of research in this article is models, methods, and procedures for designing and self-diagnosing automated models of logic control devices implemented in SoCs. The object of work is the procedures for automated design and diagnosis of digital devices on the SoC technology platform. The aim of the study is to develop models and procedures for designing and self-testing in the cycle of automated design of automatic logic control systems on the SoC technology platform, which will significantly increase the reliability of their operation. The article solves the following tasks: consideration of the procedures for interacting the processor core with programmable logic as part of the SoC; improvement of the procedures for designing and testing software and hardware systems based on SoC; further development of procedures for automated design, verification, and diagnosis of cyber-physical logic control systems using programming languages and hardware description languages; implementation of the procedure for hardware self-testing of control automata on the SoC technology platform. The following methods are implemented: synthesis of control automata based on graph models, implementation of control automata models in the C programming language using an automata template, diagnostic experiment by traversing the automata transition graph. Results achieved. Based on the analysis of the procedures for the interaction of the processor core and programmable logic on the selected SoC platform, a model of a cyber-physical logic control system was designed. The practical implementation was carried out on the basis of the Vivado/Vitis/Vitis HLS CAD toolkit. The method of hardware self-testing of control automata on the technological platform of SoC ZYNQ-7000 was implemented. Conclusions. The article analyzes the principles of designing embedded cyber-physical systems implemented in system-on-chip. The principles of building verification systems and embedded self-diagnostics of system-on-chip systems containing software and hardware are considered. The developed methods are tested on a model of a traffic light logic control device on the SoC FPGA platform of the ZYNQ-7000 family by Xilinx. The Moore's control automaton is implemented in the PL block in the C programming language, and the operational automaton is implemented in the PS block. During the organization of the self-diagnosis process, a nondestructive diagnostic experiment was performed by traversing all arcs of the transition graph, starting from the initial vertex. In this case, the tester was an operational automaton, the reference logic and time values of which were stored in the memory of the PS unit. Visual observation of the diagnostic experiment was carried out using the LED panel of the ZedBoard board.Предметом дослідження в статті є моделі, методи та процедури проєктування та самодіагностики автоматних моделейпристроїв логічного керування, реалізованих в SoC. Об’єкт роботи – процедури автоматизованого проєктуваннята діагностування цифрових пристроїв на технологічній платформі SoC. Метою дослідження є розроблення моделейі процедур проєктування та самотестування в циклі автоматизованого проєктування автоматних систем логічного управління на технологічній платформі SoC, що суттєво підвищить надійність їх функціювання. У статті вирішуються такі завдання: розгляд процедур взаємодії процесорного ядра з програмованою логікою у складі SoC; удосконалення процедур проєктування та тестування програмно-апаратних систем на основі SoC; подальший розвиток процедур автоматизованого проєктування, верифікації та діагностування кіберфізичних систем логічного управління з використанням мов програмування та мов опису апаратури; реалізація процедури апаратного самотестування керуючих автоматів на технологічній платформі SoC. Упроваджуються такі методи: синтез керуючих автоматів на основі графових моделей, імплементація моделей керуючих автоматів мовою програмування С з використанням автоматного шаблону, діагностичний експеримент способом обходу графа переходів автомата. Досягнуті результати. На основі аналізу процедур взаємодії процесорного ядра та програмованої логіки на обраній платформі SoC спроєктовано модель кіберфізичної системи логічного управління. Практичну реалізацію виконано на базі стеку інструментальних засобів САПР Vivado/Vitis/Vitis HLS. Реалізовано метод апаратного самотестування керуючих автоматів на технологічній платформі SoC ZYNQ-7000. Висновки. У статті проаналізовано принципи проєктування вбудованих кіберфізичних систем,що реалізуються в системах на кристалі. Розглянуто принципи побудови систем верифікації та вбудованої самодіагностики систем на кристалі, що містять програмну й апаратну частини. Розроблені методи апробовано на моделі пристрою логічного керування світлофором на технологічній платформі SoC FPGA сімейства ZYNQ-7000 фірми Xilinx. Керуючий автомат Мура реалізовано у блоці PL мовою програмування С, а операційний автомат – у блоці PS.Під час організації процесу самодіагностики здійснено неруйнівний діагностичний експеримент способом обходувсіх дуг графа переходів, починаючи з початкової вершини. Тестером у цьому разі був операційний автомат, еталоннілогічні та часові значення якого зберігалися в пам’яті блока PS. Візуальне спостереження за виконанням діагностичногоексперименту здійснювалося за допомогою панелі світлодіодів плати ZedBoard

Innovative Techniques for Testing and Diagnosing SoCs

We rely upon the continued functioning of many electronic devices for our everyday welfare, usually embedding integrated circuits that are becoming even cheaper and smaller with improved features. Nowadays, microelectronics can integrate a working computer with CPU, memories, and even GPUs on a single die, namely System-On-Chip (SoC). SoCs are also employed on automotive safety-critical applications, but need to be tested thoroughly to comply with reliability standards, in particular the ISO26262 functional safety for road vehicles. The goal of this PhD. thesis is to improve SoC reliability by proposing innovative techniques for testing and diagnosing its internal modules: CPUs, memories, peripherals, and GPUs. The proposed approaches in the sequence appearing in this thesis are described as follows: 1. Embedded Memory Diagnosis: Memories are dense and complex circuits which are susceptible to design and manufacturing errors. Hence, it is important to understand the fault occurrence in the memory array. In practice, the logical and physical array representation differs due to an optimized design which adds enhancements to the device, namely scrambling. This part proposes an accurate memory diagnosis by showing the efforts of a software tool able to analyze test results, unscramble the memory array, map failing syndromes to cell locations, elaborate cumulative analysis, and elaborate a final fault model hypothesis. Several SRAM memory failing syndromes were analyzed as case studies gathered on an industrial automotive 32-bit SoC developed by STMicroelectronics. The tool displayed defects virtually, and results were confirmed by real photos taken from a microscope. 2. Functional Test Pattern Generation: The key for a successful test is the pattern applied to the device. They can be structural or functional; the former usually benefits from embedded test modules targeting manufacturing errors and is only effective before shipping the component to the client. The latter, on the other hand, can be applied during mission minimally impacting on performance but is penalized due to high generation time. However, functional test patterns may benefit for having different goals in functional mission mode. Part III of this PhD thesis proposes three different functional test pattern generation methods for CPU cores embedded in SoCs, targeting different test purposes, described as follows: a. Functional Stress Patterns: Are suitable for optimizing functional stress during I Operational-life Tests and Burn-in Screening for an optimal device reliability characterization b. Functional Power Hungry Patterns: Are suitable for determining functional peak power for strictly limiting the power of structural patterns during manufacturing tests, thus reducing premature device over-kill while delivering high test coverage c. Software-Based Self-Test Patterns: Combines the potentiality of structural patterns with functional ones, allowing its execution periodically during mission. In addition, an external hardware communicating with a devised SBST was proposed. It helps increasing in 3% the fault coverage by testing critical Hardly Functionally Testable Faults not covered by conventional SBST patterns. An automatic functional test pattern generation exploiting an evolutionary algorithm maximizing metrics related to stress, power, and fault coverage was employed in the above-mentioned approaches to quickly generate the desired patterns. The approaches were evaluated on two industrial cases developed by STMicroelectronics; 8051-based and a 32-bit Power Architecture SoCs. Results show that generation time was reduced upto 75% in comparison to older methodologies while increasing significantly the desired metrics. 3. Fault Injection in GPGPU: Fault injection mechanisms in semiconductor devices are suitable for generating structural patterns, testing and activating mitigation techniques, and validating robust hardware and software applications. GPGPUs are known for fast parallel computation used in high performance computing and advanced driver assistance where reliability is the key point. Moreover, GPGPU manufacturers do not provide design description code due to content secrecy. Therefore, commercial fault injectors using the GPGPU model is unfeasible, making radiation tests the only resource available, but are costly. In the last part of this thesis, we propose a software implemented fault injector able to inject bit-flip in memory elements of a real GPGPU. It exploits a software debugger tool and combines the C-CUDA grammar to wisely determine fault spots and apply bit-flip operations in program variables. The goal is to validate robust parallel algorithms by studying fault propagation or activating redundancy mechanisms they possibly embed. The effectiveness of the tool was evaluated on two robust applications: redundant parallel matrix multiplication and floating point Fast Fourier Transform

DeSyRe: on-Demand System Reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints

On-Line Dependability Enhancement of Multiprocessor SoCs by Resource Management

This paper describes a new approach towards dependable design of homogeneous multi-processor SoCs in an example satellite-navigation application. First, the NoC dependability is functionally verified via embedded software. Then the Xentium processor tiles are periodically verified via on-line self-testing techniques, by using a new IIP Dependability Manager. Based on the Dependability Manager results, faulty tiles are electronically excluded and replaced by fault-free spare tiles via on-line resource management. This integrated approach enables fast electronic fault detection/diagnosis and repair, and hence a high system availability. The dependability application runs in parallel with the actual application, resulting in a very dependable system. All parts have been verified by simulation

Dependable reconfigurable multi-sensor poles for security

Wireless sensor network poles for security monitoring under harsh environments require a very high dependability as they are safety-critical [1]. An example of a multi-sensor pole is shown. Crucial attribute in these systems for security, especially in harsh environment, is a high robustness and guaranteed availability during lifetime. This environment could include molest. In this paper, two approaches are used which are applied simultaneously but are developed in different projects. \u

Test exploration and validation using transaction level models

The complexity of the test infrastructure and test strategies in systems-on-chip approaches the complexity of the functional design space. This paper presents test design space exploration and validation of test strategies and schedules using transaction level models (TLMs). Since many aspects of testing involve the transfer of a significant amount of test stimuli and responses, the communication-centric view of TLMs suits this purpose exceptionally wel

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level

In recent technology nodes, reliability is considered a part of the standard design ¿ow at all levels of embedded system design. While techniques that use only low-level models at gate- and register transfer-level offer high accuracy, they are too inefficient to consider the overall application of the embedded system. Multi-level models with high abstraction are essential to efficiently evaluate the impact of physical defects on the system. This paper provides a methodology that leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction-level modeling. This way it is possible to accurately evaluate the impact of the faults on the entire hardware/software system. A case study of a system consisting of hardware and software for image compression and data encryption is presented and the method is compared to a standard gate/RT mixed-level approac