635 research outputs found
Towards Cognitive Radio for emergency networks
Large parts of the assigned spectrum is underutilized while the increasing number
of wireless multimedia applications leads to spectrum scarcity. Cognitive Radio
is an option to utilize non-used parts of the spectrum that actually are assigned to primary
services. The benefits of Cognitive Radio are clear when used in emergency
situations. Current emergency services rely much on the public networks. This is not
reliable in emergency situations, where the public networks can get overloaded. The
major limitation of emergency networks is spectrum scarcity, since multimedia data
in the emergency network needs a lot of radio resources. The idea of applying Cognitive
Radio to the emergency network is to alleviate this spectrum shortage problem
by dynamically accessing free spectrum resources. Cognitive Radio is able to work
in different frequency bands and various wireless channels and supports multimedia
services such as voice, data and video. A reconfigurable radio architecture is proposed
to enable the evolution from the traditional software defined radio to Cognitive Radio
Implementation of a Combined OFDM-Demodulation and WCDMA-Equalization Module
For a dual-mode baseband receiver for the OFDMWireless LAN andWCDMA standards, integration of the demodulation and equalization tasks on a dedicated hardware module has been investigated. For OFDM demodulation, an FFT algorithm based on cascaded twiddle factor decomposition has been selected. This type of algorithm combines high spatial and temporal regularity in the FFT data-flow graphs with a minimal number of computations. A frequency-domain algorithm based on a circulant channel approximation has been selected for WCDMA equalization. It has good performance, low hardware complexity and a low number of computations. Its main advantage is the reuse of the FFT kernel, which contributes to the integration of both tasks. The demodulation and equalization module has been described at the register transfer level with the in-house developed Arx language. The core of the module is a pipelined radix-23 butterfly combined with a complex multiplier and complex divider. The module has an area of 0.447 mm2 in 0.18 Āæm technology and a power consumption of 10.6 mW. The proposed module compares favorably with solutions reported in literature
Reconfigurable Architectures for Wireless Systems: Design Exploration and Integration Challenges
Mobile devices are severely power and area limited due to battery capacity
and system size. In many of these example systems, advanced features require
computationally complex signal processing on high-speed data streams for enhanced networking capabilities. Thus, mapping high-level communication and networking algorithms to system architectures is a complex and challenging procedure. An important challenge is to characterize the area, time, and power requirements of these embedded system modules and to use this information effectively to determine the architecture of programmable, reconfigurable, and fixed-function modules. In this paper, we will focus on application examples in wireless networking which highlight these challenges in reconfigurable systems integration.Nokia CorporationTexas Instruments IncorporatedNational Science Foundatio
VLSI Architectures and Rapid Prototyping Testbeds for Wireless Systems
The rapid evolution of wireless access is creating an ever changing variety of standards for indoor and outdoor environments. The real-time processing demands of wireless data rates in excess of 100 Mbps is a challenging problem for
architecture design and verification. In this paper, we consider current trends in VLSI architecture and in rapid prototyping testbeds to evaluate these systems. The key phases in multi-standard system design and prototyping
include: Algorithm Mapping to Parallel Architectures ā based on the real-time data and sampling rate and the resulting area, time and power complexity; Configurable Mappings and Design Exploration ā based on heterogeneous architectures consisting of DSP, programmable application-specific instruction (ASIP) processors, and co-processors; and Verification and Testbed Integration
ā based on prototype implementation on programmable devices and integration with RF units.Nokia Foundation FellowshipNokia CorporationNational InstrumentsNational Science Foundatio
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