An approach to dynamic power consumption current testing of CMOS ICs

© 1995 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.I/sub DDQ/ testing is a powerful strategy for detecting defects that do not alter the logic behavior of CMOS ICs. Such a technique is very effective especially in the detection of bridging defects although some opens can be also detected. However, an important set of open and parametric defects escape quiescent power supply current testing because they prevent current elevation. Extending the consumption current testing time, from the static period to the dynamic one (i.e. considering the transient current), defects not covered with I/sub DDQ/ can be detected. Simulations using an on-chip sensor show that this technique can reach a high coverage for defects preventing current and also for those raising the static power consumption.Peer ReviewedPostprint (published version

Test de courant de repos (I[indice]D[indice]D[indice]Q) basé sur l'analyse de testabilité et sur l'insertion des points de test pour les circuits séquentiels

Test I DDQ et les défectuosités de circuits CMOS -- Analyse de testabilité -- Insertion des points de test pour le I DDQ -- Test I DDQ -- Modèle collé simple -- Défectuosités et le modèle collé simple -- Détection des pannes avec le test I DDQ -- I DDQ et l'insertion de points de test -- I DDQ les mesures de testabilité et l'insertion de points de test -- Techniques traditionnelles -- Performances de la technique traditionnelle -- Dégradations temporelles -- Surface additionnelle -- Technique de balayage -- Description de l'outil