2,128 research outputs found
Towards Verifying Nonlinear Integer Arithmetic
We eliminate a key roadblock to efficient verification of nonlinear integer
arithmetic using CDCL SAT solvers, by showing how to construct short resolution
proofs for many properties of the most widely used multiplier circuits. Such
short proofs were conjectured not to exist. More precisely, we give n^{O(1)}
size regular resolution proofs for arbitrary degree 2 identities on array,
diagonal, and Booth multipliers and quasipolynomial- n^{O(\log n)} size proofs
for these identities on Wallace tree multipliers.Comment: Expanded and simplified with improved result
Efficient Path Delay Test Generation with Boolean Satisfiability
This dissertation focuses on improving the accuracy and efficiency of path delay test generation using a Boolean satisfiability (SAT) solver. As part of this research, one of the most commonly used SAT solvers, MiniSat, was integrated into the path delay test generator CodGen. A mixed structural-functional approach was implemented in CodGen where longest paths were detected using the K Longest Path Per Gate (KLPG) algorithm and path justification and dynamic compaction were handled with the SAT solver.
Advanced techniques were implemented in CodGen to further speed up the performance of SAT based path delay test generation using the knowledge of the circuit structure. SAT solvers are inherently circuit structure unaware, and significant speedup can be availed if structure information of the circuit is provided to the SAT solver. The advanced techniques explored include: Dynamic SAT Solving (DSS), Circuit Observability Don’t Care (Cir-ODC), SAT based static learning, dynamic learnt clause management and Approximate Observability Don’t Care (ACODC). Both ISCAS 89 and ITC 99 benchmarks as well as industrial circuits were used to demonstrate that the performance of CodGen was significantly improved with MiniSat and the use of circuit structure
Algorithmic Obfuscation for LDPC Decoders
In order to protect intellectual property against untrusted foundry, many
logic-locking schemes have been developed. The main idea of logic locking is to
insert a key-controlled block into a circuit to make the circuit function
incorrectly without right keys. However, in the case that the algorithm
implemented by the circuit is naturally fault-tolerant or self-correcting,
existing logic-locking schemes do not affect the system performance much even
if wrong keys are used. One example is low-density parity-check (LDPC)
error-correcting decoder, which has broad applications in digital
communications and storage. This paper proposes two algorithmic-level
obfuscation methods for LDPC decoders. By modifying the decoding process and
locking the stopping criterion, our new designs substantially degrade the
decoder throughput and/or error-correcting performance when the wrong key is
used. Besides, our designs are also resistant to the SAT, AppSAT and removal
attacks. For an example LDPC decoder, our proposed methods reduce the
throughput to less than 1/3 and/or increase the decoder error rate by at least
two orders of magnitude with only 0.33% area overhead
Addressing Variable Dependency in GNN-based SAT Solving
Boolean satisfiability problem (SAT) is fundamental to many applications.
Existing works have used graph neural networks (GNNs) for (approximate) SAT
solving. Typical GNN-based end-to-end SAT solvers predict SAT solutions
concurrently. We show that for a group of symmetric SAT problems, the
concurrent prediction is guaranteed to produce a wrong answer because it
neglects the dependency among Boolean variables in SAT problems. % We propose
AsymSAT, a GNN-based architecture which integrates recurrent neural networks to
generate dependent predictions for variable assignments. The experiment results
show that dependent variable prediction extends the solving capability of the
GNN-based method as it improves the number of solved SAT instances on large
test sets
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