3,193 research outputs found
An extensive English language bibliography on graph theory and its applications, supplement 1
Graph theory and its applications - bibliography, supplement
An extensive English language bibliography on graph theory and its applications
Bibliography on graph theory and its application
Optimized Compilation of Aggregated Instructions for Realistic Quantum Computers
Recent developments in engineering and algorithms have made real-world
applications in quantum computing possible in the near future. Existing quantum
programming languages and compilers use a quantum assembly language composed of
1- and 2-qubit (quantum bit) gates. Quantum compiler frameworks translate this
quantum assembly to electric signals (called control pulses) that implement the
specified computation on specific physical devices. However, there is a
mismatch between the operations defined by the 1- and 2-qubit logical ISA and
their underlying physical implementation, so the current practice of directly
translating logical instructions into control pulses results in inefficient,
high-latency programs. To address this inefficiency, we propose a universal
quantum compilation methodology that aggregates multiple logical operations
into larger units that manipulate up to 10 qubits at a time. Our methodology
then optimizes these aggregates by (1) finding commutative intermediate
operations that result in more efficient schedules and (2) creating custom
control pulses optimized for the aggregate (instead of individual 1- and
2-qubit operations). Compared to the standard gate-based compilation, the
proposed approach realizes a deeper vertical integration of high-level quantum
software and low-level, physical quantum hardware. We evaluate our approach on
important near-term quantum applications on simulations of superconducting
quantum architectures. Our proposed approach provides a mean speedup of
, with a maximum of . Because latency directly affects the
feasibility of quantum computation, our results not only improve performance
but also have the potential to enable quantum computation sooner than otherwise
possible.Comment: 13 pages, to apper in ASPLO
Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAs
In-time particle trajectory reconstruction in the Large Hadron Collider is
challenging due to the high collision rate and numerous particle hits. Using
GNN (Graph Neural Network) on FPGA has enabled superior accuracy with flexible
trajectory classification. However, existing GNN architectures have inefficient
resource usage and insufficient parallelism for edge classification. This paper
introduces a resource-efficient GNN architecture on FPGAs for low latency
particle tracking. The modular architecture facilitates design scalability to
support large graphs. Leveraging the geometric properties of hit detectors
further reduces graph complexity and resource usage. Our results on Xilinx
UltraScale+ VU9P demonstrate 1625x and 1574x performance improvement over CPU
and GPU respectively
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