Evaluation of a Field Programmable Gate Array Circuit Reconfiguration System

This research implements a circuit reconfiguration system (CRS) to reconfigure a field programmable gate array (FPGA) in response to a faulty configurable logic block (CLB). It is assumed that the location of the fault is known and the CLB is moved according to one of four replacement methods: column left, column right, row up, and row down. Partial reconfiguration of the FPGA is done through the Joint Test Action Group (JTAG) port to produce the desired logic block movement. The time required to accomplish the reconfiguration is measured for each method in both clear and congested areas of the FPGA. The measured data indicate that there is no consistently better replacement method, regardless of the circuit congestion or location within the FPGA. Thus, given a specific location in the FPGA, there is no preferred replacement method that will result in the lowest reconfiguration time

Efficient Network-Flow Based Techniques for Dynamic Fault Reconfiguration in FPGAs

In this paper, we consider a "dynamic" node covering framework for incorporating fault tolerance in SRAM-based segmented array FPGAs with spare row(s) and/or column(s) of cells. Two types of designs are considered: one that can support only node-disjoint (and hence nonintersecting) rectilinear reconfiguration paths, and the other that can support edge-disjoint (and hence possibly intersecting) rectilinear reconfiguration paths. The advantage of this approach is that reconfiguration paths are determined dynamically depending upon the actual set of faults and track segments are used as required, thus resulting in higher reconfigurability and lower track overheads compared to previously proposed "static" approaches. We provide optimal networkflow based reconfiguration algorithms for both of our designs and present and analyze a technique for speeding up these algorithms, depending upon the fault size, by as much as 20 times. Finally, we present reconfigurability results for our FPGA designs that show much better fault tolerance for them compared to previous approaches---the reconfigurability of the edge-disjoint design is 90% or better and 100% most of the time, which implies near-optimal spare-cell utilization