Efficient double fault diagnosis for CMOS logic circuits with a specific application to generic bridging faults

[[abstract]]© 2003 Institute of Information Science Academia Sinica - Fault diagnosis that predicts the most likely fault sites in a faulty chip is an important step for manufacturing yield improvement or design debugging. In this paper, we address the problem of double fault diagnosis for full-scan designs. Our algorithm aims to identify both faults accurately. The features of our algorithm include the following. (1) The proposed algorithm is not limited to any particular fault type. (2) An effective selection heuristic is incorporated to significantly reduce the diagnosis time, while retaining a high success rate of catching faults. (3) The inject-and-evaluate paradigm proposed in [6] is incorporated to accurately screen out unlikely fault candidates. Experimental results on ISCAS85 benchmark circuits injected with a generic bridging fault, two stuck-at faults, or two gate-type faults show that both faults can be caught simultaneously within several minutes with a high success rate.[[department]]電機工程學

An efficient logic fault diagnosis framework based on effect-cause approach

Fault diagnosis plays an important role in improving the circuit design process and the manufacturing yield. With the increasing number of gates in modern circuits, determining the source of failure in a defective circuit is becoming more and more challenging. In this research, we present an efficient effect-cause diagnosis framework for combinational VLSI circuits. The framework consists of three stages to obtain an accurate and reasonably precise diagnosis. First, an improved critical path tracing algorithm is proposed to identify an initial suspect list by backtracing from faulty primary outputs toward primary inputs. Compared to the traditional critical path tracing approach, our algorithm is faster and exact. Second, a novel probabilistic ranking model is applied to rank the suspects so that the most suspicious one will be ranked at or near the top. Several fast filtering methods are used to prune unrelated suspects. Finally, to refine the diagnosis, fault simulation is performed on the top suspect nets using several common fault models. The difference between the observed faulty behavior and the simulated behavior is used to rank each suspect. Experimental results on ISCAS85 benchmark circuits show that this diagnosis approach is efficient both in terms of memory space and CPU time and the diagnosis results are accurate and reasonably precise