Analysis and improvement of S-Box in Rijndael- AES algorithm

The internet has become a part of everyday life and is used as a communication tool, a way to bank, invest, shop and an educational and entertainment medium. As the importance and popularity of the internet has grown over the years, so has the number of threats from hackers on the internet which has necessitated the need for the encryption of confidential data. Various methods of data encryption have been used over time, with developments being made to improve these techniques as hackers develop improved ways of attacking the algorithms used for encryption. This process of continued improvement of cryptographic security brought about the development and acceptance of the Advanced Encryption Standard (AES), which is a National Institute of Standards and Technology specification for the encryption of electronic data including financial, telecommunications, and government data. The Rijndael algorithm was selected as the encryption algorithm for AES in October 2001 and is currently used by government agencies and the private sector to secure sensitive unclassified information. Research has shown that Rijndael is susceptible to differential/ linear cryptanalysis for 7 and 8-round Rijndael, saturation attacks, algebraic attacks and side channel attacks on reduced versions of Rijndael, which could pave the way for a full-blown attack on the Rijndael algorithm in the future. This research investigates the weaknesses present in the Rijndael algorithm using various custom-made testing tools and then using the results of this investigation to improve the security of the algorithm. The improvement is provided in the form a technique of generating highly non-linear output using a non-linear random number generator which uses the recursive inverse congruential method. The research will comprise of three phases; literature review, analysis of the Rijndael algorithm using custom-made tools and development of an improvement whose performance will be evaluated in comparison to the current algorithm

Vortex: A New Family of One Way Hash Functions based on Rijndael Rounds and Carry-less Multiplication

We present Vortex a new family of one way hash functions that can produce message digests of 224, 256, 384 and 512 bits. The main idea behind the design of these hash functions is that we use well known algorithms that can support very fast diffusion in a small number of steps. We also balance the cryptographic strength that comes from iterating block cipher rounds with SBox substitution and diffusion (like Whirlpool) against the need to have a lightweight implementation with as small number of rounds as possible. We use a variable number of Rijndael rounds with a stronger key schedule. Our goal is not to protect a secret symmetric key but to support perfect mixing of the bits of the input into the hash value. Rijndael rounds are followed by our variant of Galois Field multiplication. This achieves cross-mixing between 128-bit or 256-bit sets. Our hash function uses the Enveloped Merkle-Damgard construction to support properties such as collision resistance, first and second pre-image resistance, pseudorandom oracle preservation and pseudorandom function preservation. We provide analytical results that demonstrate that the number of queries required for finding a collision with probability greater or equal to 0.5 in an ideal block cipher approximation of Vortex 256 is at least 1.18x2^122.55 if the attacker uses randomly selected message words. We also provide experimental results that indicate that the compression function of Vortex is not inferior to that of the SHA family regarding its capability to preserve the pseudorandom oracle property. We list a number of well known attacks and discuss how the Vortex design addresses them. The main strength of the Vortex design is that this hash function can demonstrate an expected performance of 2.2-2.5 cycles per byte in future processors with instruction set support for Rijndael rounds and carry-less multiplication. We provide arguments why we believe this is a trend in the industry. We also discuss how optimized assembly code can be written that demonstrates such performance

Smart Card DBMS: where are we now?

Smart card is today the most widespread secured portable computing device. Four years ago, we addressed the problem of scaling down database techniques for the smart card and we proposed the design of what we called a PicoDBMS, a full-fledged database system embedded in a smart card. Since then, thanks to the hardware progress and to the joint implementation efforts of our team and our industrial partner, this utopian design gave birth to a complete prototype running on an experimental smart card platform. This paper revisits the problem statement in the light of the hardware and applications evolution. Then, it introduces a benchmark dedicated to Pico–style databases and provides an extensive performance analysis of our prototype, discussing lessons learned at experimentation time and helping selecting the appropriate storage and indexation model for a given class of embedded applications. Finally, it draws new research perspectives for data management on secured chips (smart cards, USB dongles, multimedia rendering devices, smart objects in an ambient intelligence surrounding)

Efficient AES implementations for ARM based platforms

The Advanced Encryption Standard (AES) contest, started by the U.S. National Institute of Standards and Technology (NIST), saw the Rijndael algorithm as its winner. Although the AES is fully defined in terms of functionality, it requires best exploitation of architectural parameters in order to reach the optimum performance on specific architectures. Our work concentrates on ARM cores widely used in the embedded industry. Most promising implementation choices for the common ARM Instruction Set Architecture (ISA) are identified, and a new implementation for the linear mixing layer is proposed. The performance improvement over current implementations is demonstrated by a case study on the Intel StrongARM SA-1110 Microprocessor. Further improvements based on exploitation of memory hierarchies are also described, and the corresponding performance figures are presented