23 research outputs found

    An efficient graph representation for arithmetic circuit verification

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    *PHDD: an efficient graph representation for floating point circuit verification

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    Mapping switch-level simulation onto gate-level hardware accelerators

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    In this paper, we present a framework for performing switch-level simulation on hardware accelerators

    Formal verification of an ARM processor

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    A Methodology for Hardware Verification Based on Logic Simulation.

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    A Distributed Genetic Algorithm Solution to the Boolean Satisfiability Problem

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    This paper attempts to improve the solution of the NP complete Boolean Satisfiability (BSAT) problem by partitioning the task into three sub-tasks and distributing them over an experimental 3-node Distributed Computing System (DCS). A genetic algorithm (GA) has been used to consider multiple feasible solutions. The GA based algorithm is applied to the standard BSAT benchmarks on a single computer and on DCS configuration using non-optimised and optimised executables. The task is coarsely partitioned and distributed over the DCS using the Simple Object Access Protocol (SOAP) technology. The results reveal that the DCS enabled solution exhibits better performance than a single computer configuration for non-optimised GA code. However, no clear correlation could be identified between the single computer and the DCS for the optimised version of the GA search. The main contribution of this investigation is the design of a GA based solution to the BSAT problem for DCS

    Resolvedor SAT, basado en procedimientos Davis-Putnam-Longemann-Loveland

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    El problema de satisfaci贸n de f贸rmulas l贸gicas (SAT), es un problema NP-Hard. Una forma de resolverlo es por medio de procedimientos Davis-Putnam-Longemann-Loveland (DPLL), ahora presentamos una implementaci贸n de un resolvedor SAT a partir de procedimientos DPLL.The problem of SAT is a problem NP-HARD, a way for solve is by Davis-Putnam-Longemann_Lovelan procedure (DPLL), here there is a SAT solver by this type of procedurePostprint (published version

    Board-level multiterminal net assignment

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    Graph Symmetry Detection and Canonical Labeling: Differences and Synergies

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    Symmetries of combinatorial objects are known to complicate search algorithms, but such obstacles can often be removed by detecting symmetries early and discarding symmetric subproblems. Canonical labeling of combinatorial objects facilitates easy equivalence checking through quick matching. All existing canonical labeling software also finds symmetries, but the fastest symmetry-finding software does not perform canonical labeling. In this work, we contrast the two problems and dissect typical algorithms to identify their similarities and differences. We then develop a novel approach to canonical labeling where symmetries are found first and then used to speed up the canonical labeling algorithms. Empirical results show that this approach outperforms state-of-the-art canonical labelers.Comment: 15 pages, 10 figures, 1 table, Turing-10
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