3 research outputs found
ΠΠ²ΠΎΠΉΠ½ΠΎΠ΅ ΠΊΠΎΠ΄ΠΈΡΠΎΠ²Π°Π½ΠΈΠ΅ ΡΠΎΡΡΠΎΡΠ½ΠΈΠΉ Π² ΡΠΎΠ²ΠΌΠ΅ΡΠ΅Π½Π½ΠΎΠΌ Π°Π²ΡΠΎΠΌΠ°ΡΠ΅
ΠΡΠ΅Π΄Π»ΠΎΠΆΠ΅Π½ ΠΌΠ΅ΡΠΎΠ΄ ΡΠΌΠ΅Π½ΡΡΠ΅Π½ΠΈΡ Π°ΠΏΠΏΠ°ΡΠ°ΡΡΡΠ½ΡΡ
Π·Π°ΡΡΠ°Ρ Π² ΡΡ
Π΅ΠΌΠ΅ ΡΠΎΠ²ΠΌΠ΅ΡΠ΅Π½Π½ΠΎΠ³ΠΎ ΠΌΠΈΠΊΡΠΎΠΏΡΠΎΠ³ΡΠ°ΠΌΠΌΠ½ΠΎΠ³ΠΎ Π°Π²ΡΠΎΠΌΠ°ΡΠ°, ΡΠ΅Π°Π»ΠΈΠ·ΡΠ΅ΠΌΠΎΠ³ΠΎ Π² Π±Π°Π·ΠΈΡΠ΅ FPGA. ΠΠ΅ΡΠΎΠ΄ ΠΎΡΠ½ΠΎΠ²Π°Π½ Π½Π° ΡΠ°Π·Π±ΠΈΠ΅Π½ΠΈΠΈ ΠΌΠ½ΠΎΠΆΠ΅ΡΡΠ²Π° ΡΠΎΡΡΠΎΡΠ½ΠΈΠΉ Π½Π° ΠΊΠ»Π°ΡΡΡ, ΠΊΠ°ΠΆΠ΄ΡΠΉ ΠΈΠ· ΠΊΠΎΡΠΎΡΡΡ
ΡΠΎΠΎΡΠ²Π΅ΡΡΡΠ²ΡΠ΅Ρ ΠΎΡΠ΄Π΅Π»ΡΠ½ΠΎΠΌΡ Π±Π»ΠΎΠΊΡ ΡΡ
Π΅ΠΌΡ. Π’Π°ΠΊΠΎΠΉ ΠΏΠΎΠ΄Ρ
ΠΎΠ΄ ΠΏΡΠΈΠ²ΠΎΠ΄ΠΈΡ ΠΊ ΡΡ
Π΅ΠΌΠ°ΠΌ Ρ ΡΠ΅Π³ΡΠ»ΡΡΠ½ΠΎΠΉ ΡΡΡΡΠΊΡΡΡΠΎΠΉ ΠΈ ΡΡΠ΅ΠΌΡ Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΈΠΌΠΈ ΡΡΠΎΠ²Π½ΡΠΌΠΈ. ΠΡΠΈΠ²Π΅Π΄Π΅Π½ ΠΏΡΠΈΠΌΠ΅Ρ ΡΠΈΠ½ΡΠ΅Π·Π° ΡΡ
Π΅ΠΌΡ Π°Π²ΡΠΎΠΌΠ°ΡΠ° Ρ ΠΈΡΠΏΠΎΠ»ΡΠ·ΠΎΠ²Π°Π½ΠΈΠ΅ΠΌ ΠΏΡΠ΅Π΄Π»ΠΎΠΆΠ΅Π½Π½ΠΎΠ³ΠΎ ΠΌΠ΅ΡΠΎΠ΄Π°. ΠΠΎΠΊΠ°Π·Π°Π½Ρ ΡΡΠ»ΠΎΠ²ΠΈΡ Π΅Π³ΠΎ ΠΏΡΠΈΠΌΠ΅Π½Π΅Π½ΠΈΡ.Π£ ΡΡΠ°ΡΡΡ Π·Π°ΠΏΡΠΎΠΏΠΎΠ½ΠΎΠ²Π°Π½ΠΎ ΠΌΠ΅ΡΠΎΠ΄ Π·ΠΌΠ΅Π½ΡΠ΅Π½Π½Ρ Π°ΠΏΠ°ΡΠ°ΡΡΡΠ½ΠΈΡ
Π²ΠΈΡΡΠ°Ρ ΠΏΡΠΈ ΡΠΎΠ·ΡΠΎΠ±ΡΡ ΠΏΡΠΈΡΡΡΠΎΡΠ² ΡΠΏΡΠ°Π²Π»ΡΠ½Π½Ρ ΡΠΈΡΡΠΎΠ²ΠΈΡ
ΡΠΈΡΡΠ΅ΠΌ. ΠΠ½ΠΈΠΆΠ΅Π½Π½Ρ Π²ΠΈΡΡΠ°Ρ Π°ΠΏΠ°ΡΠ°ΡΡΡΠΈ Π΄ΠΎΠ·Π²ΠΎΠ»ΡΡ ΠΏΡΠ΄Π²ΠΈΡΠΈΡΠΈ ΡΠΊΡΡΡΡ ΡΠΈΡΡΠΎΠ²ΠΎΡ ΡΠΈΡΡΠ΅ΠΌΠΈ Π·Π° ΡΠ°Ρ
ΡΠ½ΠΎΠΊ Π·ΠΌΠ΅Π½ΡΠ΅Π½Π½Ρ ΠΏΠ»ΠΎΡΡ ΠΊΡΠΈΡΡΠ°Π»Π° ΠΠΠΠ‘, Π·Π½ΠΈΠΆΠ΅Π½Π½Ρ ΡΠΏΠΎΠΆΠΈΠ²Π°Π½Π½Ρ Π΅Π½Π΅ΡΠ³ΡΡ ΡΠ° ΠΏΡΠ΄Π²ΠΈΡΠ΅Π½Π½Ρ ΡΠ²ΠΈΠ΄ΠΊΠΎΠ΄ΡΡ. ΠΠ΅ΡΠΎΠ΄ Π·Π°ΡΠ½ΠΎΠ²Π°Π½ΠΈΠΉ Π½Π° ΡΠΎΠ·Π±ΠΈΡΡΡ ΠΌΠ½ΠΎΠΆΠΈΠ½ΠΈ ΡΡΠ°Π½ΡΠ² Π°Π²ΡΠΎΠΌΠ°ΡΠ° Π½Π° ΠΊΠ»Π°ΡΠΈ, ΠΊΠΎΠΆΠ΅Π½ Π· ΡΠΊΠΈΡ
Π²ΡΠ΄ΠΏΠΎΠ²ΡΠ΄Π°Ρ ΠΎΠΊΡΠ΅ΠΌΠΎΠΌΡ Π±Π»ΠΎΠΊΡ ΡΡ
Π΅ΠΌΠΈ. Π’Π°ΠΊΠΈΠΉ ΠΏΡΠ΄Ρ
ΡΠ΄ ΠΏΡΠΈΠ·Π²ΠΎΠ΄ΠΈΡΡ Π΄ΠΎ ΡΡ
Π΅ΠΌ Π· ΡΠ΅Π³ΡΠ»ΡΡΠ½ΠΎΡ ΡΡΡΡΠΊΡΡΡΠΎΡ Ρ ΡΡΡΠΎΠΌΠ° Π»ΠΎΠ³ΡΡΠ½ΠΈΠΌΠΈ ΡΡΠ²Π½ΡΠΌΠΈ. Π£ ΡΡΠ°ΡΡΡ Π½Π°Π²Π΅Π΄Π΅Π½ΠΎ ΠΏΡΠΈΠΊΠ»Π°Π΄ ΡΠΈΠ½ΡΠ΅Π·Ρ ΡΡ
Π΅ΠΌΠΈ Π°Π²ΡΠΎΠΌΠ°ΡΠ° Π· Π²ΠΈΠΊΠΎΡΠΈΡΡΠ°Π½Π½ΡΠΌ Π·Π°ΠΏΡΠΎΠΏΠΎΠ½ΠΎΠ²Π°Π½ΠΎΠ³ΠΎ ΠΌΠ΅ΡΠΎΠ΄Ρ. ΠΠΎΠΊΠ°Π·Π°Π½Ρ ΡΠΌΠΎΠ²ΠΈ ΠΉΠΎΠ³ΠΎ Π·Π°ΡΡΠΎΡΡΠ²Π°Π½Π½Ρ.The article proposes a method of reducing hardware costs in the development of control devices for digital systems. Reducing hardware costs can improve the quality of a digital system by reducing the size of the VLSI chip, reducing energy consumption and increasing speed. The method is based on splitting the set of states of an automaton into classes, each of which corresponds to a separate block of the circuit. This approach leads to circuit with a regular structure having three levels of logic. The article provides an example of the synthesis of an automaton circuit using the proposed method. The conditions of its application are shown
Effective and efficient FPGA synthesis through general functional decomposition
In this paper, a new information-driven circuit synthesis method is discussed that targets LUT-based FPGAs and FPGA-based reconfigurable system-on-a-chip platforms. The method is based on the bottomβup general functional decomposition and theory of information relationship measures that we previously developed. It differs considerably from all other known methods. The experimental results from the automatic circuit synthesis tool that implements the method clearly demonstrate that the information-driven general functional decomposition based on information relationship measures efficiently produces very fast and compact FPGA circuits