Dry etching of metallization

The production dry etch processes are reviewed from the perspective of microelectronic fabrication applications. The major dry etch processes used in the fabrication of microelectronic devices can be divided into two categories - plasma processes in which samples are directly exposed to an electrical discharge, and ion beam processes in which samples are etched by a beam of ions extracted from a discharge. The plasma etch processes can be distinguished by the degree to which ion bombardment contributes to the etch process. This, in turn is related to capability for anisotropic etching. Reactive Ion Etching (RIE) and Ion Beam Etching are of most interest for etching of thin film metals. RIE is generally considered the best process for large volume, anisotropic aluminum etching

Deemo: a new technology for the fabrication of microstructures

The recent innovations in dry etching make it a promising technology for the fabrications of micromoulds. The high aspect ratios, directional freedom, low roughness, high etch rates and high selectivity with respect to the mask material allow a versatile fabrication process of micromoulds for subsequent electroplating and embossing, as is demonstrated with the DEEMO process. DEEMO is an English acronym and stands for Dry Etching, Electroplating and Moulding

(Invited) towards a vertical and damage free post-etch InGaAs fin profile: dry etch processing, sidewall damage assessment and mitigation options

Based on current projections, III-Vs are expected to replace Si as the n-channel solution in FinFETs at the 7nm technology node. The realisation of III-V FinFETs entails top-down fabrication via dry etch techniques. Vertical fins in conjunction with high quality sidewall MOS interfaces are required for high-performance logic devices. This, however, is difficult to achieve with dry etching. Highly anisotropic etching required of vertical fins is concomitant with increased damage to the sidewalls, resulting in the quality of the sidewall MOS interface being compromised. In this work, we address this challenge in two stages by first undertaking a systematic investigation of dry etch processing for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. In the second stage, dry etch process optimisation and post-etch sidewall passivation schemes are explored to mitigate the damage arising from anisotropic etching required for the realisation of vertical fins

Progress towards photonic crystal quantum cascade laser

The work describes recent progress in the design, simulation, implementation and characterisation of photonic crystal (PhC) GaAs-based quantum cascade lasers (QCLs). The benefits of applying active PhC confinement around a QCL cavity are explained, highlighting a route to reduced threshold current operation. Design of a suitable PhC has been performed using published bandgap maps; simulation results of this PhC show a wide, high reflectivity stopband. Implementation of the PhC for the device is particularly difficult, requiring a very durable metallic dry etch mask, high performance dry etching and a low damage epilayer-down device mounting technique. Preliminary shallow etched PhC QCLs demonstrated the viability of current injection through the metal etch mask and the device mounting technique. Development of the etch mask and dry etching have demonstrated a process suitable for the manufacture of deep etched PhC structures. All the necessary elements for implementing deep etched PhC QCLs have now been demonstrated, allowing for the development of high performance devices

Low temperature sacrificial wafer bonding for planarization after very deep etching

A new technique, at temperatures of 150°C or 450°C, that provides planarization after a very deep etching step in silicon is presented. Resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique contains a wafer bond step followed by an etch back. Results of (1) polymer bonding followed by dry etching and (2) anodic bonding combined with KOH etching are discussed. The polymer bond method was applied in a strain based membrane pressure sensor to pattern the strain gauges and to provide electrical connections across a deep corrugation in a thin silicon nitride membrane by metal bridge

Si and GaAs dry etching utilizing showered electron-beam assisted etching through Cl2 gas

Electron-beam (EB) dry etching for Si and GaAs has been studied by utilizing showered electron-beam assisted etching in the presence of Cl 2 gas. Anisotropic etching has been demonstrated for both Si and GaAs EB dry etching. Si and GaAs patterns with 0.6 and 0.3 μm linewidths have been obtained at a dose of 2×10-2 C/cm2 and 1×10-3 C/cm2. It was confirmed, through measuring photoluminescence, that damage induced by EB dry etching is nearly the same as that caused by gas etching and less than damage induced by reactive ion-beam etching and ion-beam etching.Matsui S., Watanabe H.. Si and GaAs dry etching utilizing showered electron-beam assisted etching through Cl2 gas. Applied Physics Letters, 59, 18, 2284. https://doi.org/10.1063/1.106044