A high resolution full-field range imaging system for robotic devices

There has been considerable effort by many researchers to develop a high resolution full-field range imaging system. Traditionally these systems rely on a homodyne technique that modulates the illumination source and shutter speed at some high frequency. These systems tend to suffer from the need to be calibrated to account for changing ambient light conditions and generally cannot provide better than single centimeter range resolution, and even then over a range of only a few meters. We present a system, tested to proof-of-concept stage that is being developed for use on a range of mobile robots. The system has the potential for real-time, sub millimeter range resolution, with minimal power and space requirements

Digital Frequency Domain Multiplexer for mm-Wavelength Telescopes

An FPGA based digital signal processing (DSP) system for biasing and reading out multiplexed bolometric detectors for mm-wavelength telescopes is presented. This readout system is being deployed for balloon-borne and ground based cosmology experiments with the primary goal of measuring the signature of inflation with the Cosmic Microwave Background Radiation. The system consists of analog superconducting electronics running at 250mK and 4K, coupled to digital room temperature backend electronics described here. The digital electronics perform the real time functionality with DSP algorithms implemented in firmware. A soft embedded processor provides all of the slow housekeeping control and communications. Each board in the system synthesizes multi-frequency combs of 8 to 32 carriers in the MHz band to bias the detectors. After the carriers have been modulated with the sky-signal by the detectors, the same boards digitize the comb directly. The carriers are mixed down to base-band and low pass filtered. The signal bandwidth of 0.050 Hz - 100 Hz places extreme requirements on stability and requires powerful filtering techniques to recover the sky-signal from the MHz carriers.Comment: 6 pages, 6 figures, Submitted May 2007 to IEEE Transactions on Nuclear Science (TNS

Design techniques for low-power wide-band direct digital frequency synthesizers of spread spectrum communication applications

For frequency agile communication systems, fast frequency switching in fine frequency steps with good spectral purity is crucial. Direct Digital Frequency Synthesizer (DDFS) is best suitable for these applications, but is not widely employed in wireless communication systems due to its high power consumption. In general, low power and high integration design are two challenges for mixed signal-circuits and communication systems designers. In this dissertation, new design techniques for DDFS at both architecture and circuit levels are proposed and investigated in order to minimize power consumption and optimize performance. A ROM-less low power wide band DDFS prototype using segmented sine wave Digital-to-Analog Converter (DAC) were designed, fabricated and tested to demonstrate the new design techniques.;First, to further reduce power consumption and save chip area, two new phase interpolation ROM less DDFS architectures are proposed. Segmentation technique is applied to the design of sine wave DAC for DDFS: (1) based upon trigonometric identities, a segmented sine wave DAC with fine nonlinear interpolation DAC\u27s is proposed; (2) based upon first order Taylor series and simple linear interpolation, a segmented sine wave DAC with a fine linear interpolation DAC is proposed. Second, a figure of merit (FM) is defined to find the optimal sine wave DAC segmentations for various resolutions of the segmented sine wave DAC\u27s. The device mismatch effects on the performance of segmented sine wave were also discussed. Third, For DDFS using current-steering segmented sine wave DAC with 12-b phase resolution and 11-b amplitude resolution, a behavioral model in Verilog was used to verify the functionality and validate the architecture. Finally, a DDFS prototype was designed and fabricated in a standard 0.25mum CMOS process. The measured SFDR is better than 50 dB with output frequencies up to 3/8 of the 300 MHz clock frequency. The prototype occupies an active area of 1.4 mm2 and consumes 240 mW for 300 MHz clock frequency. The new techniques reduce the power dissipation and die area substantially when compared to conventional ROM based DDFS designs with on-chip DAC

Direct Digital Frequency Synthesizer Architecture for Wireless Communication in 90 NM CMOS Technology

Software radio is one promising field that can meet the demands for low cost, low power, and high speed electronic devices for wireless communication. At the heart of software radio is a programmable oscillator called a Direct Digital Synthesizer (DDS). DDS has the capabilities of rapid frequency hopping by digital software control while operating at very high frequencies and having sub-hertz resolution. Nevertheless, the digital-to-analog converter (DAC) and the read-only-memory (ROM) look-up table, building blocks of the DDS, prevent the DDS to be used in wireless communication because they introduce errors and noises to the DDS and their performances deteriorate at high speed. The DAC and ROM are replaced in this thesis by analog active filters that convert the square wave output of the phase accumulator directly into a sine wave. The proposed architecture operates with a reference clock of 9.09 GHz and can be fully-integrated in 90 nm CMOS technology

Sound and Automated Synthesis of Digital Stabilizing Controllers for Continuous Plants

Modern control is implemented with digital microcontrollers, embedded within a dynamical plant that represents physical components. We present a new algorithm based on counter-example guided inductive synthesis that automates the design of digital controllers that are correct by construction. The synthesis result is sound with respect to the complete range of approximations, including time discretization, quantization effects, and finite-precision arithmetic and its rounding errors. We have implemented our new algorithm in a tool called DSSynth, and are able to automatically generate stable controllers for a set of intricate plant models taken from the literature within minutes.Comment: 10 page

실시간 근거리 영상화를 위한 MIMO 역합성 개구 레이더 시스템

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 남상욱.Microwave and millimeter wave (micro/mmW) imaging systems have advantages over other imaging systems in that they have penetration properties over non-metallic structures and non-ionization. However, these systems are commercially applicable in limited areas. Depending on the quality and size of the images, a system can be expensive and images cannot be provided in real-time. To overcome the challenges of the current micro/mmW imaging system, it is critical to suggest a new system concept and prove its potential benefits and hazards by demonstrating the testbed. This dissertation presents Ku1DMIC, a wide-band micro/mmW imaging system using Ku-band and 1D-MIMO array, which can overcome the challenges above. For cost-effective 3D imaging capabilities, Ku1DMIC uses 1D-MIMO array configuration and inverse synthetic aperture radar (ISAR) technique. At the same time, Ku1DMIC supports real-time data acquisition through a system-level design of a seamless interface with frequency modulated continuous wave (FMCW) radar. To show the feasibility of 3D imaging with Ku1DMIC and its real-time capabilities, an accelerated imaging algorithm, 1D-MIMO-ISAR RSA, is proposed and demonstrated. The detailed contributions of the dissertation are as follows. First, this dissertation presents Ku1DMIC – a Ku-band MIMO frequency-modulated continuous-wave (FMCW) radar experimental platform with real-time 2D near-field imaging capabilities. The proposed system uses Ku-band to cover the wider illumination area given the limited number of antennas and uses a fast ramp and wide-band FMCW waveform for rapid radar data acquisition while providing high-resolution images. The key design aspect behind the platform is stability, reconfigurability, and real-time capabilities, which allows investigating the exploration of the system’s strengths and weaknesses. To satisfy the design aspect, a digitally assisted platform is proposed and realized based on an AMD-Xilinx UltraScale+ Radio Frequency System on Chip (RFSoC). The experimental investigation for real-time 2D imaging has proved the ability of video-rate imaging at around 60 frames per second. Second, a waveform digital pre-distortion (DPD) method and calibration method are proposed to enhance the image quality. Even if a clean FMCW waveform is generated with the aid of the optimized waveform generator, the signal will inevitably suffer from distortion, especially in the RF subsystem of the platform. In near-field imaging applications, the waveform DPD is not effective at suppressing distortion in wide-band FMCW radar systems. To solve this issue, the LO-DPD architecture and binary search based DPD algorithm are proposed to make the waveform DPD effective in Ku1DMIC. Furthermore, an image-domain optimization correction method is proposed to compensate for the remaining errors that cannot be eliminated by the waveform DPD. For robustness to various unwanted signals such as noise and clutter signals, two regularized least squares problems are applied and compared: the generalized Tikhonov regularization and the total variation (TV) regularization. Through various 2D imaging experiments, it is confirmed that both methods can enhance the image quality by reducing the sidelobe level. Lastly, the research is conducted to realize real-time 3D imaging by applying the ISAR technique to Ku1DMIC. The realization of real-time 3D imaging using 1D-MIMO array configuration is impactful in that this configuration can significantly reduce the costs of the 3D imaging system and enable imaging of moving objects. To this end, the signal model for the 1D-MIMO-ISAR configuration is presented, and then the 1D-MIMO-ISAR range stacking algorithm (RSA) is proposed to accelerate the imaging reconstruction process. The proposed 1D-MIMO-ISAR RSA can reconstruct images within hundreds of milliseconds while maintaining almost the same image quality as the back-projection algorithm, bringing potential use for real-time 3D imaging. It also describes strategies for setting ROI, considering the real-world situations in which objects enter and exit the field of view, and allocating GPU memory. Extensive simulations and experiments have demonstrated the feasibility and potential benefits of 1D-MIMO-IASR configuration and 1D-MIMO-ISAR RSA.마이크로파 및 밀리미터파(micro/mmW) 영상화 시스템은 비금속 구조 및 비이온화에 비해 침투 특성이 있다는 점에서 다른 이미징 시스템에 비해 장점이 있다. 그러나 이러한 시스템은 제한된 영역에서만 상업적으로 적용되고 있다. 이미지의 품질과 크기에 따라 시스템이 매우 고가일 수 있으며 이미지를 실시간으로 제공할 수 없는 현황이다. 현재의 micro/mmW 이미징 시스템의 문제를 극복하려면 새로운 시스템 개념을 제안하고 테스트베드를 시연하여 잠재적인 이점과 위험을 입증하는 것이 중요하다. 본 논문에서는 Ku-band와 1D-MIMO 어레이를 이용한 광대역 micro/mmW 이미징 시스템인 Ku1DMIC를 제안하여 위와 같은 문제점을 극복할 수 있다. 비용 효율적인 3차원 영상화 기능을 위해 Ku1DMIC는 1D-MIMO 배열 기술과 ISAR(Inverse Synthetic Aperture Radar) 기술을 사용한다. 동시에 Ku1DMIC는 주파수 변조 연속파 (FMCW) 레이더와의 원활한 인터페이스의 시스템 수준 설계를 통해 실시간 데이터 수집을 지원한다. Ku1DMIC를 사용한 3차원 영상화의 구현 및 실시간 기능의 가능성을 보여주기 위해, 2차원 영상화를 위한 1D-MIMO RSA과 3차원 영상화를 위한 1D-MIMO-ISAR RSA가 제안되고 Ku1DMIC에서 구현된다. 따라서, 본 학위 논문의 주요 기여는 Ku-band 1D-MIMO 배열 기반 영상화 시스템 프로토타입을 개발 및 테스트하고, ISAR 기반 3차원 영상화 기능을 검사하고, 실시간 3차원 영상화 가능성을 조사하는 것이다. 이에 대한 세부적인 기여 항목은 다음과 같다. 첫째, 실시간 2D 근거리장 이미징 기능을 갖춘 Ku 대역 MIMO 주파수 변조 연속파(FMCW) 레이더 실험 플랫폼인 Ku1DMIC를 제시한다. 제안하는 시스템은 제한된 수의 안테나에서 더 넓은 조명 영역을 커버하기 위해 Ku 대역을 사용하고 고해상도 이미지를 제공하면서 빠른 레이더 데이터 수집을 위해 고속 램프 및 광대역 FMCW 파형을 사용한다. 플랫폼의 핵심 설계 원칙은 안정성, 재구성 가능성 및 실시간 기능으로 시스템의 강점과 약점을 광범위하게 탐색한다. 설계 원칙을 만족시키기 위해 AMD-Xilinx UltraScale+ RFSoC(Radio Frequency System on Chip)를 기반으로 디지털 지원 플랫폼을 제안하고 구현한다. 실시간 2D 이미징에 대한 실험적 조사는 초당 약 60프레임에서 비디오 속도 이미징의 능력을 입증했다. 둘째, 영상 품질 향상을 위한 파형 디지털 전치왜곡(DPD) 방법과 보정 방법을 제안한다. 최적화된 파형 발생기의 도움으로 깨끗한 FMCW 파형이 생성되더라도 특히 플랫폼의 RF 하위 시스템에서 신호는 필연적으로 왜곡을 겪게된다. 근거리 영상화 응용 분야에서는 파형 DPD는 광대역 FMCW 레이더 시스템의 왜곡을 억제하는 데 효과적이지 않다. 이 문제를 해결하기 위해 Ku1DMIC에서 파형 DPD가 유효하도록 LO-DPD 아키텍처와 이진 탐색 기반 DPD 알고리즘을 제안한다. 또한, 파형 DPD로 제거할 수 없는 나머지 오류를 보상하기 위해 이미지 영역 최적화 보정 방법을 제안한다. 노이즈 및 클러터 신호와 같은 다양한 원치 않는 신호에 대한 견고성을 위해 일반화된 Tikhonov 정규화 및 전체 변동(TV) 정규화라는 두 가지 정규화된 최소 자승 문제를 적용 후 비교한다. 다양한 2차원 영상화 실험을 통해 두 방법 모두 부엽 레벨을 줄여 화질을 향상시킬 수 있음을 확인한다. 마지막으로, ISAR 기법을 2차원 영상 플랫폼에 적용하여 실시간 3차원 영상을 구현하기 위한 연구를 진행한다. 1D-MIMO-ISAR 구성에서 실시간 3D 이미징의 구현은 이러한 구성이 3D 이미징 시스템의 비용을 크게 줄일 수 있다는 점에서 영향력이 있다. 따라서 이 논문에서는 1D-MIMO-ISAR 구성에 대한 이미징 재구성을 가속화하기 위해 1D-MIMO-ISAR 범위 스태킹 알고리즘(RSA)을 제안한다. 제안된 1D-MIMO-ISAR RSA는 널리 알려진 Back-Projection 알고리즘과 거의 동일한 이미지 품질을 유지하면서도 수백 밀리초 이내에 이미지를 재구성함으로써 실시간 영상화에 대한 가능성을 보여준다. 또한 물체가 시야에 들어오고 나가는 실제 상황을 고려하기 위한 ROI 설정, 그리고 메모리 할당에 대한 전략을 설명한다. 광범위한 시뮬레이션과 실험을 통해 1D-MIMO-IASR 구성 및 1D-MIMO-ISAR RSA의 가능성과 잠재적 이점을 확인한다.1 INTRODUCTION 1 1.1 Microwave and millimeter-wave imaging 1 1.2 Imaging with radar system 2 1.3 Challenges and motivation 5 1.4 Outline of the dissertation 8 2 FUNDAMENTAL OF TWO-DIMENSIONAL IMAGING USING A MIMO RADAR 9 2.1 Signal model 9 2.2 Consideration of waveform 12 2.3 Image reconstruction algorithm 16 2.3.1 Back-projection algorithm 16 2.3.2 1D-MIMO range-migration algorithm 20 2.3.3 1D-MIMO range stacking algorithm 27 2.4 Sampling criteria and resolution 31 2.5 Simulation results 36 3 MIMO-FMCW RADAR IMPLEMENTATION WITH 16 TX - 16 RX ONE- DIMENSIONAL ARRAYS 46 3.1 Wide-band FMCW waveform generator architecture 46 3.2 Overall system architecture 48 3.3 Antenna and RF transceiver module 53 3.4 Wide-band FMCW waveform generator 55 3.5 FPGA-based digital hardware design 63 3.6 System integration and software design 71 3.7 Testing and measurement 75 3.7.1 Chirp waveform measurement 75 3.7.2 Range profile measurement 77 3.7.3 2-D imaging test 79 4 METHODS OF IMAGE QUALITY ENHANCEMENT 84 4.1 Signal model 84 4.2 Digital pre-distortion of chirp signal 86 4.2.1 Proposed DPD hardware system 86 4.2.2 Proposed DPD algorithm 88 4.2.3 Measurement results 90 4.3 Robust calibration method for signal distortion 97 4.3.1 Signal model 98 4.3.2 Problem formulation 99 4.3.3 Measurement results 105 5 THREE-DIMENSIONAL IMAGING USING 1-D ARRAY SYSTEM AND ISAR TECHNIQUE 110 5.1 Formulation for 1D-MIMO-ISAR RSA 111 5.2 Algorithm implementation 114 5.3 Simulation results 120 5.4 Experimental results 122 6 CONCLUSIONS AND FUTURE WORK 127 6.1 Conclusions 127 6.2 Future work 129 6.2.1 Effects of antenna polarization in the Ku-band 129 6.2.2 Forward-looking near-field ISAR configuration 130 6.2.3 Estimation of the movement errors in ISAR configuration 131 Abstract (In Korean) 145 Acknowlegement 148박

Design and Implementation of an RF Front-End for Software Defined Radios

Software Defined Radios have brought a major reformation in the design standards for radios, in which a large portion of the functionality is implemented through pro­ grammable signal processing devices, giving the radio the ability to change its op­ erating parameters to accommodate new features and capabilities. A software radio approach reduces the content of radio frequency and other analog components of the traditional radios and emphasizes digital signal processing to enhance overall receiver flexibility. Field Programmable Gate Arrays (FPGA) are a suitable technology for the hardware platform as they offer the potential of hardware-like performance coupled with software-like programmability. Software defined radio is a very broad field, encompassing the design of various technologies all the way from the antenna to RF, IF, and baseband digital design. The RF section primarily consists of analog hardware modules. The IF and baseband sections are primarily digital. It is the general process of the radio to convert the incoming signal from RF to IF and then IF to baseband for better signal processing system. In this thesis, some of major building blocks of a Software defined radio are de­ signed and implemented using FPGAs. The design of a Digital front end, which provides the bridge between the baseband and analog RF portions of a wireless receiver, is synthesized. The Digital front end receiver consists of a digital down converter(DDC) which in turn comprises of a direct digital frequency synthesizer (DDFS), a phase accumulator and a low pass filter. The signal processing block of the DDFS is executed using Co-ordinate Rotation Digital Computer (CORDIC) iii Abstract algorithm. Cascaded-Integrator-Comb filters (CIC) are implemented for changing the sample rate of the incoming data. Application of a DDC includes software ra­ dios, multicarrier, multimode digital receivers, micro and pico cell systems,broadband data applications, instrumentation and test equipment and in-building wireless tele­ phony. Also, in this thesis, interfaces for connecting Texas Instruments high speed and high resolution Analog-to-Digital converters (ADC) and Digital-to-Analog converters (DAC) with Xilinx Virtex-5 FPGAs are also implemented and demonstrated

Techniques for Wideband All Digital Polar Transmission

abstract: Modern Communication systems are progressively moving towards all-digital transmitters (ADTs) due to their high efficiency and potentially large frequency range. While significant work has been done on individual blocks within the ADT, there are few to no full systems designs at this point in time. The goal of this work is to provide a set of multiple novel block architectures which will allow for greater cohesion between the various ADT blocks. Furthermore, the design of these architectures are expected to focus on the practicalities of system design, such as regulatory compliance, which here to date has largely been neglected by the academic community. Amongst these techniques are a novel upconverted phase modulation, polyphase harmonic cancellation, and process voltage and temperature (PVT) invariant Delta Sigma phase interpolation. It will be shown in this work that the implementation of the aforementioned architectures allows ADTs to be designed with state of the art size, power, and accuracy levels, all while maintaining PVT insensitivity. Due to the significant performance enhancement over previously published works, this work presents the first feasible ADT architecture suitable for widespread commercial deployment.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201