Adaptive Baseband Pro cessing and Configurable Hardware for Wireless Communication

The world of information is literally at one’s fingertips, allowing access to previously unimaginable amounts of data, thanks to advances in wireless communication. The growing demand for high speed data has necessitated theuse of wider bandwidths, and wireless technologies such as Multiple-InputMultiple-Output (MIMO) have been adopted to increase spectral efficiency.These advanced communication technologies require sophisticated signal processing, often leading to higher power consumption and reduced battery life.Therefore, increasing energy efficiency of baseband hardware for MIMO signal processing has become extremely vital. High Quality of Service (QoS)requirements invariably lead to a larger number of computations and a higherpower dissipation. However, recognizing the dynamic nature of the wirelesscommunication medium in which only some channel scenarios require complexsignal processing, and that not all situations call for high data rates, allowsthe use of an adaptive channel aware signal processing strategy to provide adesired QoS. Information such as interference conditions, coherence bandwidthand Signal to Noise Ratio (SNR) can be used to reduce algorithmic computations in favorable channels. Hardware circuits which run these algorithmsneed flexibility and easy reconfigurability to switch between multiple designsfor different parameters. These parameters can be used to tune the operations of different components in a receiver based on feedback from the digitalbaseband. This dissertation focuses on the optimization of digital basebandcircuitry of receivers which use feedback to trade power and performance. Aco-optimization approach, where designs are optimized starting from the algorithmic stage through the hardware architectural stage to the final circuitimplementation is adopted to realize energy efficient digital baseband hardwarefor mobile 4G devices. These concepts are also extended to the next generation5G systems where the energy efficiency of the base station is improved.This work includes six papers that examine digital circuits in MIMO wireless receivers. Several key blocks in these receiver include analog circuits thathave residual non-linearities, leading to signal intermodulation and distortion.Paper-I introduces a digital technique to detect such non-linearities and calibrate analog circuits to improve signal quality. The concept of a digital nonlinearity tuning system developed in Paper-I is implemented and demonstratedin hardware. The performance of this implementation is tested with an analogchannel select filter, and results are presented in Paper-II. MIMO systems suchas the ones used in 4G, may employ QR Decomposition (QRD) processors tosimplify the implementation of tree search based signal detectors. However,the small form factor of the mobile device increases spatial correlation, whichis detrimental to signal multiplexing. Consequently, a QRD processor capableof handling high spatial correlation is presented in Paper-III. The algorithm and hardware implementation are optimized for carrier aggregation, which increases requirements on signal processing throughput, leading to higher powerdissipation. Paper-IV presents a method to perform channel-aware processingwith a simple interpolation strategy to adaptively reduce QRD computationcount. Channel properties such as coherence bandwidth and SNR are used toreduce multiplications by 40% to 80%. These concepts are extended to usetime domain correlation properties, and a full QRD processor for 4G systemsfabricated in 28 nm FD-SOI technology is presented in Paper-V. The designis implemented with a configurable architecture and measurements show thatcircuit tuning results in a highly energy efficient processor, requiring 0.2 nJ to1.3 nJ for each QRD. Finally, these adaptive channel-aware signal processingconcepts are examined in the scope of the next generation of communicationsystems. Massive MIMO systems increase spectral efficiency by using a largenumber of antennas at the base station. Consequently, the signal processingat the base station has a high computational count. Paper-VI presents a configurable detection scheme which reduces this complexity by using techniquessuch as selective user detection and interpolation based signal processing. Hardware is optimized for resource sharing, resulting in a highly reconfigurable andenergy efficient uplink signal detector

Design of energy efficient high speed I/O interfaces

Energy efficiency has become a key performance metric for wireline high speed I/O interfaces. Consequently, design of low power I/O interfaces has garnered large interest that has mostly been focused on active power reduction techniques at peak data rate. In practice, most systems exhibit a wide range of data transfer patterns. As a result, low energy per bit operation at peak data rate does not necessarily translate to overall low energy operation. Therefore, I/O interfaces that can scale their power consumption with data rate requirement are desirable. Rapid on-off I/O interfaces have a potential to scale power with data rate requirements without severely affecting either latency or the throughput of the I/O interface. In this work, we explore circuit techniques for designing rapid on-off high speed wireline I/O interfaces and digital fractional-N PLLs. A burst-mode transmitter suitable for rapid on-off I/O interfaces is presented that achieves 6 ns turn-on time by utilizing a fast frequency settling ring oscillator in digital multiplying delay-locked loop and a rapid on-off biasing scheme for current mode output driver. Fabricated in 90 nm CMOS process, the prototype achieves 2.29 mW/Gb/s energy efficiency at peak data rate of 8 Gb/s. A 125X (8 Gb/s to 64 Mb/s) change in effective data rate results in 67X (18.29 mW to 0.27 mW) change in transmitter power consumption corresponding to only 2X (2.29 mW/Gb/s to 4.24 mW/Gb/s) degradation in energy efficiency for 32-byte long data bursts. We also present an analytical bit error rate (BER) computation technique for this transmitter under rapid on-off operation, which uses MDLL settling measurement data in conjunction with always-on transmitter measurements. This technique indicates that the BER bathtub width for 10^(−12) BER is 0.65 UI and 0.72 UI during rapid on-off operation and always-on operation, respectively. Next, a pulse response estimation-based technique is proposed enabling burst-mode operation for baud-rate sampling receivers that operate over high loss channels. Such receivers typically employ discrete time equalization to combat inter-symbol interference. Implementation details are provided for a receiver chip, fabricated in 65nm CMOS technology, that demonstrates efficacy of the proposed technique. A low complexity pulse response estimation technique is also presented for low power receivers that do not employ discrete time equalizers. We also present techniques for implementation of highly digital fractional-N PLL employing a phase interpolator based fractional divider to improve the quantization noise shaping properties of a 1-bit ∆Σ frequency-to-digital converter. Fabricated in 65nm CMOS process, the prototype calibration-free fractional-N Type-II PLL employs the proposed frequency-to-digital converter in place of a high resolution time-to-digital converter and achieves 848 fs rms integrated jitter (1 kHz-30 MHz) and -101 dBc/Hz in-band phase noise while generating 5.054 GHz output from 31.25 MHz input

FMCW Signals for Radar Imaging and Channel Sounding

A linear / stepped frequency modulated continuous wave (FMCW) signal has for a long time been used in radar and channel sounding. A novel FMCW waveform known as “Gated FMCW” signal is proposed in this thesis for the suppression of strong undesired signals in microwave radar applications, such as: through-the-wall, ground penetrating, and medical imaging radar. In these applications the crosstalk signal between antennas and the reflections form the early interface (wall, ground surface, or skin respectively) are much stronger in magnitude compared to the backscattered signal from the target. Consequently, if not suppressed they overshadow the target’s return making detection a difficult task. Moreover, these strong unwanted reflections limit the radar’s dynamic range and might saturate or block the receiver causing the reflection from actual targets (especially targets with low radar cross section) to appear as noise. The effectiveness of the proposed waveform as a suppression technique was investigated in various radar scenarios, through numerical simulations and experiments. Comparisons of the radar images obtained for the radar system operating with the standard linear FMCW signal and with the proposed Gated FMCW waveform are also made. In addition to the radar work the application of FMCW signals to radio propagation measurements and channel characterisation in the 60 GHz and 2-6 GHz frequency bands in indoor and outdoor environments is described. The data are used to predict the bit error rate performance of the in-house built measurement based channel simulator and the results are compared with the theoretical multipath channel simulator available in Matlab

FPGA를 이용한 시간 기반 고집적 PET 데이터 수집 장치

학위논문(박사)--서울대학교 대학원 :의과대학 의과학과,2019. 8. 이재성.Positron emission tomography (PET) is a widely used functional imaging device for diagnosing cancer and neurodegenerative diseases. PET instrumentation studies focus on improving both spatial resolution and sensitivity to improve the lesion detectability while reducing radiation exposure to patients. The silicon photomultiplier (SiPM) is a photosensor suitable for high-performance PET scanners owing to its compact size and fast response. However, the SiPM-based PET scanners require a large number of readout channels owing to a high level of granularity. For example, the typical whole-body PET scanners require more than 40,000 SiPM channels. Therefore, the highly integrated data acquisition (DAQ) system that can digitize a large number of SiPM signal with preserving its fast temporal response is required to develop the high-performance SiPM-based PET scanners. Time-based signal digitization is a promising method to develop highly integrated DAQ systems owing to its simple circuitry and fast temporal response. In this thesis, studies on developing highly integrated DAQ systems using a field-programmable gate array (FPGA) were presented. Firstly, a 10-ps time-to-digital converter (TDC) implemented within the FPGA was developed. The FPGA-TDCs suffer from the non-linearity, because FPGAs are not originally designed to implement TDC. We proposed the dual-phase sampling architecture considering the FPGA clock distribution network to mitigate the TDC non-linearity. In addition, we developed the on-the-fly calibrator that compensated the innate bin width variations without introducing the dead time. Secondly, the time-based SiPM multiplexing and readout method was developed using the principle of the global positioning system (GPS). The signal traces connecting every SiPM to four timing channels were used to encode the position information. The position information was obtained using the innate transit time differences measured by four FPGA-TDCs. In addition, the minimal signal distortion by multiplexing circuit allowed to use a time-over-threshold (ToT) method for energy measurement after multiplexing. Thirdly, we proposed a new FPGA-only digitizer. The programmable FPGA input/output (I/O) port was configured with stub-series terminated logic (SSTL) input receiver, and each FPGA I/O port functioned as a high-performance voltage comparator with a fast temporal response. We demonstrated that the FPGA can be used as a high-performance DAQ system by directly digitizing the time-of-flight (TOF) PET detector signals using the FPGA without any front-end electronics. Lastly, we developed comparator-less charge-to-time converter (QTC) DAQ systems to collect data from a prototype high-resolution brain PET scanner. The energy channel consisted of a QTC combined with the SSTL input receiver of the FPGA. The timing channel was a TDC implemented within the same FPGA. The detailed structure of brain phantom was well-resolved using the developed high-resolution brain PET scanner and the highly-integrated time-based DAQ systems.양전자방출단층촬영 (Positron Emission Tomography; PET) 장치는 암과 신경퇴행성 질환을 영상화하는 데 널리 쓰이는 기능 영상장치이다. 최근 PET 스캐너 연구는 공간 분해능과 장비 민감도를 높여 병변의 진단을 쉽게 하면서 환자의 방사선 피폭을 줄이는 방법에 초점을 맞추고 있다. 실리콘 관증배기 (silicon photomultiplier; SiPM)은 크기가 작고 반응속도가 빠르기 때문에 고성능 PET 스캐너에 적합한 광검출소자이다. 하지만 SiPM 기반 PET 스캐너는 개별 SiPM의 크기가 작기 때문에 수많은 데이터 수집 채널이 필요하다. 예를 들어, 전신 PET 스캐너를 SiPM으로 구성할 경우 40,000개 이상의 SiPM 소자가 필요하다. 따라서, SiPM의 성능을 유지하면서 다채널 신호 디지털화가 가능한 고집적 데이터 수집장치 (data acquisition; DAQ)가 고성능 SiPM PET 스캐너 개발에 필요하다. 시간 기반 신호 디지털 방법은 단순한 회로와 빠른 반응속도 덕분에 고집적 DAQ 시스템을 구현하는 유망한 방법이다. 본 학위논문에서는 프로그램 가능 게이트 배열 (field-programmable gate array; FPGA)을 이용하여 고집적 DAQ 시스템을 개발하는 연구내용을 다룬다. 첫째로, 10 ps 의 분해능을 갖는 FPGA 기반 시간-디지털 변환기 (time-to-digital converter; TDC)를 개발하였다. FPGA는 TDC 구현을 위한 집적소자가 아니므로 FPGA에 구현된 TDC는 일반적으로 비선형성 문제를 가진다. 이를 해결하기 위해 비선형성 문제를 야기하는 FPGA의 클락 신호 분배 구조를 고려하여 이중 위상 샘플링 방법을 제안하였다. 또한, FPGA TDC 고유의 불균일한 분해능을 측정하고 보상하기 위하여 실시간 보정기술을 개발하였다. 둘째로, GPS 원리를 사용한 시간 기반 신호 부호화 (multiplexing) 및 수집 방법을 개발하였다. 부호화 회로는 SiPM을 네 개의 시간 수집 채널로 연결한 도선으로 구성되고 위치정보는 각 SiPM으로부터 네 개의 시간 수집 채널까지의 고유한 도파시간 차이를 계산해서 수집할 수 있다. 또한, 기존 전하 분배 부호화 회로와 달리 신호가 왜곡되지 않기 때문에 문턱 전압 방법 (time-over-threshold; ToT) 방식으로 에너지를 수집하는 것이 가능하였다. 셋째로, FPGA만으로 아날로그 신호를 디지털화 하는 새로운 방법을 개발하였다. FPGA의 프로그램 가능 입출력포트를 stub-series terminated logic (SSTL) 수신기로 프로그램하면, 각각의 FPGA 입출력포트가 빠른 시간 반응성을 가진 고성능 전압비교기로 동작한다. 비정시간 (time-of-flight; TOF) 측정 가능 PET 검출기의 신호를 전단회로 없이 FPGA만으로 디지털화하여 FPGA를 고성능 DAQ 장치로 사용할 수 있음을 입증하였다. 마지막으로, 공간분해능이 뛰어난 뇌전용 스캐너로부터 데이터를 수집하기 위해 전압비교기를 사용하지 않는 시간 기반 DAQ 장치를 개발하였다. 에너지 측정 채널은 시간-전하 변환기 (charge-to-time converter; QTC)와 FPGA의 SSTL 수신기로 구성하였다. 시각 측정 채널은 FPGA 기반 TDC로 구성하였다. 개발한 뇌전용 스캐너와 고집적 시간 기반 DAQ 장치로 획득한 뇌모양 팬텀의 자세한 구조들은 잘 구분되었다.Chapter 1. Introduction 1 1.1. Background 1 1.1.1. Positron Emission Tomography 1 1.1.2. Silicon Photomultiplier 1 1.1.3. Data Acquisition System 2 1.1.4. Time-based Signal Digitization Method 3 1.2. Purpose of Research 6 Chapter 2. FPGA-based Time-to-Digital Converter 8 2.1. Background 8 2.2. Materials and Methods 9 2.2.1. Tapped-Delay-Line TDC 9 2.2.2. FPGA 11 2.2.3. Dual-Phase TDL TDC with On-the-Fly Calibrator 11 2.2.3.1. FPGA Clock Distribution Network 11 2.2.3.2. The Principle of Dual-Phase TDL TDC 14 2.2.3.3. The Principle of Pipelined On-the-Fly Calibrator 16 2.2.3.4. Implementation of Dual-Phase TDL TDC with On-the-Fly Calibrator 18 2.2.4. Experimental Setups and Data Processing 20 2.2.4.1. TDC Characteristics 21 2.2.4.2. Arrival Time Difference Measurements 22 2.3. Results 24 2.3.1. TDC Characteristics 24 2.3.2. Arrival Time Difference Measurements 25 2.4. Discussion 28 Chapter 3. Time-based Multiplexing Method 29 3.1. Background 29 3.2. Materials and Methods 30 3.2.1. Delay Grid Multiplexing 30 3.2.2. Detector for Concept Verification 32 3.2.3. Front-end Electronics 34 3.2.4. Experimental Setups 35 3.2.4.1. Data Acquisition Using the Waveform Digitizer 37 3.2.4.2. Data Acquisition Using the FPGA-TDC 37 3.2.5. Data Processing and Analysis 38 3.2.5.1. Waveform Digitizer 38 3.2.5.2. FPGA-TDC 41 3.3. Results 44 3.3.1. Waveform Digitizer 44 3.3.1.1. Waveform, Rise Time, and Decay Time 44 3.3.1.2. Flood Map 46 3.3.1.3. Energy 48 3.3.1.4. CTR 49 3.3.2. FPGA-TDC 50 3.3.2.1. ToT and Energy 50 3.3.2.2. Flood Map 51 3.3.2.3. CTR 52 3.4. Discussion 53 Chapter 4. FPGA-Only Signal Digitization Method 54 4.1. Background 54 4.2. Materials and Methods 56 4.2.1. Single-ended Memory Interface Input Receiver 56 4.2.2. SeMI Digitizer 56 4.2.3. Experimental Setup for Intrinsic Performance Characterization 59 4.2.3.1. ToT 59 4.2.3.2. Timing 60 4.2.4. Experimental Setup for Individual Signal Digitization 60 4.2.4.1. TOF PET Detector 60 4.2.4.2. Data Acquisition Using the Waveform Digitizer 61 4.2.4.3. Data Acquisition Using the SeMI Digitizer 63 4.2.4.4. Data Analysis 63 4.3. Results 64 4.3.1. Results of Intrinsic Performance Characterization 64 4.3.1.1. ToT 64 4.3.1.2. Timing 65 4.3.2. Results of Individual Signal Digitization 66 4.3.2.1. Energy 66 4.3.2.2. CTR 67 4.4. Discussion 68 Chapter 5. Comparator-less QTC DAQ Systems for High-Resolution Brain PET Scanners 70 5.1. Background 70 5.2. Materials and Methods 72 5.2.1. Brain PET Scanner 72 5.2.1.1. Block Detector 72 5.2.1.2. Sector 73 5.2.1.3. Scanner Geometry 74 5.2.2. Comparator-less QTC DAQ System 75 5.2.3. Data Acquisition Chain of Brain PET Scanner 79 5.2.4. Experimental Setups and Data Processing 79 5.2.4.1. Energy Linearity 79 5.2.4.2. Performance Evaluation of Block Detector 80 5.2.4.3. Phantom Studies 82 5.3. Results 83 5.3.1. Energy Linearity 83 5.3.2. Performance Evaluation of Block Detector 83 5.3.3. Phantom Studies 85 5.4. Discussion 87 Chapter 6. Conclusions 89 Bibliography 90 Abstract in Korean (국문 초록) 94Docto

Low-Cost Inventions and Patents

Inventions have led to the technological advances of mankind. There are inventions of all kinds, some of which have lasted hundreds of years or even longer. Low-cost technologies are expected to be easy to build, have little or no energy consumption, and be easy to maintain and operate. The use of sustainable technologies is essential in order to move towards a greater global coverage of technology, and therefore to improve human quality of life. Low-cost products always respond to a specific need, even if no in-depth analysis of the situation or possible solutions has been carried out. It is a consensus in all industrialized countries that patents have a decisive influence on the organization of the economy, as they are a key element in promoting technological innovation. Patents must aim to promote the technological development of countries, starting from their industrial situations

Shuttle synthetic aperture radar implementation study, volume 1

Results of an implementation study for a synthetic aperture radar for the space shuttle orbiter are described. The overall effort was directed toward the determination of the feasibility and usefulness of a multifrequency, multipolarization imaging radar for the shuttle orbiter. The radar is intended for earth resource monitoring as well as oceanographic and marine studies

Architectures and Novel Functionalities for Optical Access OFDM Networks "Arquitecturas y Nuevas Funcionalidades para Redes OFDM de Acceso Óptico"

En los últimos años ha habido un gran aumento en el despliegue de redes de acceso ópticas de fibra hasta el hogar (FTTH, del inglés fibre-to-the home). FTTH es una solución flexible, una tecnología de acceso de futuro que permite proporcionar tasas de datos del orden de Gbit/s por ususario. Diversos estudios indican que FTTH se convertirá en la diferencia clave entre los operadores más importantes. Además, FTTH es la única tecnolotgía capaz de crear nuevas fuentes de ingresos de aplicaciones de alta velocidad, como por ejemple entretenimiento de alta definición (vído y juegos de alta definición...) Dede el punto de vista del operador, una de las vientajas importantes que proporciona FTTH es que permite una mayor eficiencia operativa en coparción con otras tecnologías de acceso, principalmente por la reducción de costes de mantenimiento y de operación. Además, FTTH reduce los requisitos de los equipos de las centrales. Esta tesis doctoral tiene como ojetivo extender estas ventajas más allá del concepto FTTH mediante la integración de la red óptica de distribución desplegada dentro del hogar así como el enlace radio final de corto o medio alcance inalámbrico. Esto proporciona una arquitctura de red FFTH integrada de extremo a extremo. De este modo, los beneficios de la reducción de costes operativos y mayor eficiencia se extienden hasta el usuario final de la red. En esta tesis doctoral, se propone una arqutectura de acceso integrada óptica-radio basada en la multiplexación por división ortogonal de fecuencia (OFDM, del inglés orthogonal frequency división multiplexing) para proporcionar diferentes servicios al usuario como Internet, teléfono/voz, televisión de lata definición, conexión inalámbrica y seguridad en el hogar. Las señales OFDM se utilizan en muchos estándares inalámbricos como las señales de banda ultraancha (UWB, del inglés ultra-wide band), WiMAX, LTE, WLAN, DVB-T o DAB. Estos formatos aprovechan las características intrínsecas de la modulación OFDM como su mayor inmunidad ante desvanecimiento multi-camino. Esta tesis incluye la propuesta y la demostración experimental de la transmisión simultánea y bi-direccional de señales OFDM multi-estándar en radio-sobre-fibra proporcionando servicios triple-play basados en OFDM como UWB para televisión de alta definición, WiMAX para datos de Internet, y LTE para el servicio telefónico.Morant Perez, M. (2012). Architectures and Novel Functionalities for Optical Access OFDM Networks "Arquitecturas y Nuevas Funcionalidades para Redes OFDM de Acceso Óptico" [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/15076Palanci

Design and implementation of a modular controller for robotic machines

This research focused on the design and implementation of an Intelligent Modular Controller (IMC) architecture designed to be reconfigurable over a robust network. The design incorporates novel communication, hardware, and software architectures. This was motivated by current industrial needs for distributed control systems due to growing demand for less complexity, more processing power, flexibility, and greater fault tolerance. To this end, three main contributions were made. Most distributed control architectures depend on multi-tier heterogeneous communication networks requiring linking devices and/or complex middleware. In this study, first, a communication architecture was proposed and implemented with a homogenous network employing the ubiquitous Ethernet for both real-time and non real-time communication. This was achieved by a producer-consumer coordination model for real-time data communication over a segmented network, and a client-server model for point-to-point transactions. The protocols deployed use a Time-Triggered (TT) approach to schedule real-time tasks on the network. Unlike other TT approaches, the scheduling mechanism does not need to be configured explicitly when controller nodes are added or removed. An implicit clock synchronization technique was also developed to complement the architecture. Second, a reconfigurable mechanism based on an auto-configuration protocol was developed. Modules on the network use this protocol to automatically detect themselves, establish communication, and negotiate for a desired configuration. Third, the research demonstrated hardware/software co-design as a contribution to the growing discipline of mechatronics. The IMC consists of a motion controller board designed and prototyped in-house, and a Java microcontroller. An IMC is mapped to each machine/robot axis, and an additional IMC can be configured to serve as a real-time coordinator. The entire architecture was implemented in Java, thus reinforcing uniformity, simplicity, modularity, and openness. Evaluation results showed the potential of the flexible controller to meet medium to high performance machining requirements

Doppler compensation algorithms for DSP-based implementation of OFDM underwater acoustic communication systems

In recent years, orthogonal frequency division multiplexing (OFDM) has gained considerable attention in the development of underwater communication (UWC) systems for civilian and military applications. However, the wideband nature of the communication links necessitate robust algorithms to combat the consequences of severe channel conditions such as frequency selectivity, ambient noise, severe multipath and Doppler Effect due to velocity change between the transmitter and receiver. This velocity perturbation comprises two scenarios; the first induces constant time scale expansion/compression or zero acceleration during the transmitted packet time, and the second is time varying Doppler-shift. The latter is an increasingly important area in autonomous underwater vehicle (AUV) applications. The aim of this thesis is to design a low complexity OFDM-based receiver structure for underwater communication that tackles the inherent Doppler effect and is applicable for developing real-time systems on a digital signal processor (DSP). The proposed structure presents a paradigm in modem design from previous generations of single carrier receivers employing computationally expensive equalizers. The thesis demonstrates the issues related to designing a practical OFDM system, such as channel coding and peak-to-average power ratio (PAPR). In channel coding, the proposed algorithms employ convolutional bit-interleaved coded modulation with iterative decoding (BICM-ID) to obtain a higher degree of protection against power fading caused by the channel. A novel receiver structure that combines an adaptive Doppler-shift correction and BICM-ID for multi-carrier systems is presented. In addition, the selective mapping (SLM) technique has been utilized for PAPR. Due to their time varying and frequency selective channel nature, the proposed systems are investigated via both laboratory simulations and experiments conducted in the North Sea off the UK’s North East coast. The results of the study show that the proposed systems outperform block-based Doppler-shift compensation and are capable of tracking the Doppler-shift at acceleration up to 1m /s2.EThOS - Electronic Theses Online ServiceIraqi Government's Ministry of Higher Education and Scientific ResearchGBUnited Kingdo