Digital aspect clock

Digital clock precisely set and reset by pulses from a solar sensor, combined with a logic system, provides accurate time-sector division of spin-stabilized satellite. Integral times for viewing physical phenomena from various directions are equal and mean angles of viewing can be determined

All-digital self-adaptive PVTA variation aware clock generation system for DFS

An all-digital self-adaptive clock generation system capable of adapt the clock frequency to compensate the effects of PVTA variations on the IC propagation delay and satisfy an externally set propagation length condition is presented. The design uses time-to-digital converters (TDCs) to measure the propagation length and a variable length ring oscillator (VLRO) to synthesize the clock signal. The VLRO naturally adapts its frequency to the PVTA variations suffered by its logic gates while the TDCs are used to track these variations across the chip and modify the VLRO length in order to adapt the clock frequency to them. The system measurements, for a 45nm FPGA, show that it adapts the VLRO length, and therefore the clock frequency, to satisfy the propagation length condition. Measurements also prove the system capabilities to act as a dynamic frequency scaling clock source since the propagation length condition value act as a frequency selection input and a strong linear relation between the input value and the resultant clock period is present.Peer ReviewedPostprint (author’s final draft

Phase Locked Loop Test Methodology

Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications

Decimal digit generator for commutated data: A Concept

Perform analog-to-digital conversion on input signal with staircase circuit having 10% resolution, convert digital result to analog voltage, subtract it from original input signal; read out feedback signals as decimal digit representation during one clock phase and servo-error difference between input and feedback as analog portion during following clock phase

Open loop digital frequency multiplier

An open loop digital frequency multiplier is described which has a multiplied output synchronized to low frequency clock pulse. The system includes a multistage digital counter which provides a pulse output as a function of an integer divisor. The integer divisor and the timing or counting cycle of the counter are interrelated to the frequency of a clock input. The counting cycle is controlled by a one shot multivibrator which, in turn, is driven by a reference frequency input

Single-clock-cycle two-dimensional median filter

Median filters are of interest to image processing due to their ability to remove impulsive noise. Conventional digital implementations of the median function, however, require multiple clock cycles, a number that is proportional to the size of the 2-D data block. We present in the Letter a complete CMOS implementation, which consumes very little power and computes the median in just one clock cycle, independently from the size of the data block

Third order digital-to-analog converter

System, consisting of sample and hold digital-to-analog converter, clock circuit, sample delay circuit, initial condition circuit and interpolator circuit, improves accuracy of reconstructed analog signal without increasing sample rates

Multiplexer uses insulated gate-field effect transistors

Small lightweight multiplexer incorporates IG-FETs /Insulated Gate-Field Effect Transistors/ for all digital logic functions, including the internally generated 3.6-kHz clock. It consists of 30 primary channels, each of which is sampled 120 times per second