Circuit solutions to compensate for device degradation in analog design in scaled technologies

The continued aggressive scaling of semiconductor devices has had detrimental effects on the performance of those devices as used in analog circuitry. Specifically, the maximum intrinsic gain (MIG) of the devices continues to degrade as the device channel lengths are reduced below 100 nm and beyond. MIG is shown to degrade from 21.6 dB in a 180 nm technology to 12.2 dB in a 65 nm technology despite the application of traditional design techniques including device size scaling and bias voltage increases. This reduction in MIG along with other process scaling effects significantly complicates the design of linear amplifiers in these technologies. This work proposes the use of positive feedback to compensate for MIG degradation in linear amplifier design in scaled technologies. Criteria for stable and process tolerant design are derived and examined in the context of amplifier models of varying degrees of complexity. This analysis defines an all-encompassing positive feedback design methodology for use in linear amplifier design of low-gain high-frequency amplifier design. Additionally, the effects of positive feedback are compared and contrasted to the effects of the commonly studied negative feedback design methodology. Finally, the methodology is applied to a differential amplifier stage in TSMC\u27s 65 nm process using standard threshold voltage, thin oxide CMOS devices. These amplifiers were fabricated and tested to validate the positive feedback design methodology. Simulation shows that 98.4% of positive feedback amplifiers have improved gain over the baseline differential amplifier with an average improvement in gain of 10.3 dB. Silicon measurements of the amplifier gain show improvements of 17.1 dB on average. Similar to the application of negative feedback, gain improvement is achieved at the cost of frequency response. The gain-bandwidth product of the amplifier is reduced by an average of 18.4 GHz from 44.6 GHz. The circuitry required to implement this technique represent a meager 6% increase in silicon area from 460 μm2 to 488 μm2

Plasmonic color filter array, high performance analog to digital converter architectures and novel circuit techniques

Part I: Plasmonic color filters can be manufactured at lower cost since they can be fabricated in single lithographic process step as compared to Fabry-Perot based filters. In addition, they have narrow passband making resolving sharp features in sample spectrum possible. Due to these benefits, in this thesis, Plasmonic color filters are investigated as alternative to conventional color filters and their feasibility for spectroscopy demonstrated through reconstruction of 6 sample spectra by using a set of 20 color filters. The error in reconstructed sample spectra is less than 0.137 root mean squared error across all samples. Part II: A novel 12-bit pipelined successive approximation analog to digital converter is investigated for high speed data conversion. The design was implemented in TSMC 65nm process to demonstrate the feasibility of the architecture. Furthermore, a high dynamic range audio delta sigma modulator using pseudo-pseudo differential topology was investigated and feasibility simulated using TSMC 65nm process. In addition, various novel systems and circuit techniques including efficient calibration of feedback digital to analog converters, new boosted switch and push-pull source follower circuits were investigated to improve upon existing circuit topologies