Diagnosing Single Faults in Fanout-Free Combinational Circuits

We show how to construct, in a simple manner, a test set having n + 1 tests for a fanout-free combinational circuit with n primary inputs which distinguishes (diagnoses) nonequivalent single faults. This result is an improvement over the upper bound in [1, Theorem 3.9] of n + g (g is the number of primary input gates) and the upper bound in [3, Theorem 4], [5] of 2n for the least number of tests required to distinguish among nonequivalent single faults

An emulation-based methodology for integrating design, testing and diagnosis of application-specific integrated circuits

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (p. 106).by Guru Sivaraman.M.S