Open source microprocessor and on-chip-bus for system-on-chip

A System-On-Chip (SoC) is a complex integrated circuit that combines blocks of processor, memory and peripheral devices in one chip. SoCs often form the main or the only component of embedded systems. The advantages of the SoC include improvements in performance, size, reliability, power dissipation, cost, and design turn-around time. The hardware blocks – sometimes referred to as intellectual property cores or just IPs – are connected using a proprietary or open on-chip bus (OCB). The SoCs may be fabricated as application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). The non-recurring engineering (NRE) costs for ASICs are much higher although the unit cost for the finished product is lower. For simpler designs and/or lower production runs, FPGAs are usually more cost-effective. One of the costs in implementing an SoC is acquiring the source code or designing the required cores. An approach for reducing costs is to use open source hardware. Open source cores have the advantages of zero license and royalty cost, ability to modify the cores at will, no limitation on supply and maintenance, portability and simplified prototyping. We discuss our implementation of a skeleton SoC incorporating a DLX processor, the Wishbone on-chip bus, and a memory system. The processor bus- memory combination forms a foundation to which a designer can add more cores such as memory and peripherals as long as they comply with the Wishbone protocol. The DLX processor and memory are described in VHDL, while the Wishbone module is in Verilog HDL. Quartus II software is used to synthesize, compile and verify the functionality of CPU and Wishbone by simulation and timing analysis. The partial SoC system is implemented in Altera APEX20KE200 FPGA board. Nios, which is the core processor in the FPGA board, is used as an intermediate processor which communicates with DLX and the rest of the system via Avalon Bus Protocol to verify system operation and functionality in real hardware environment

A Scalable Unsegmented Multiport Memory for FPGA-Based Systems

On-chip multiport memory cores are crucial primitives for many modern high-performance reconfigurable architectures and multicore systems. Previous approaches for scaling memory cores come at the cost of operating frequency, communication overhead, and logic resources without increasing the storage capacity of the memory. In this paper, we present two approaches for designing multiport memory cores that are suitable for reconfigurable accelerators with substantial on-chip memory or complex communication. Our design approaches tackle these challenges by banking RAM blocks and utilizing interconnect networks which allows scaling without sacrificing logic resources. With banking, memory congestion is unavoidable and we evaluate our multiport memory cores under different memory access patterns to gain insights about different design trade-offs. We demonstrate our implementation with up to 256 memory ports using a Xilinx Virtex-7 FPGA. Our experimental results report high throughput memories with resource usage that scales with the number of ports

An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links

As semiconductor technologies continues to scale, more and more cores are being integrated on the same multicore chip. This increase in complexity poses the challenge of efficient data transfer between these cores. Several on-chip network architectures are proposed to improve the design flexibility and communication efficiency of such multicore chips. However, in a larger system consisting of several multicore chips across a board or in a System-in-Package (SiP), the performance is limited by the communication among and within these chips. Such systems, most commonly found within computing modules in typical data center nodes or server racks, are in dire need of an efficient interconnection architecture. Conventional interchip communication using wireline links involve routing the data from the internal cores to the peripheral I/O ports, travelling over the interchip channels to the destination chip, and finally getting routed from the I/O to the internal cores there. This multihop communication increases latency and energy consumption while decreasing data bandwidth in a multichip system. Furthermore, the intrachip and interchip communication architectures are separately designed to maximize design flexibility. Jointly designing them could, however, improve the communication efficiency significantly and yield better solutions. Previous attempts at this include an all-photonic approach that provides a unified inter/intra-chip optical network, based on recent progress in nano-photonic technologies. Works on wireless inter-chip interconnects successfully yielded better results than their wired counterparts, but their scopes were limited to establishing a single wireless connection between two chips rather than a communication architecture for a system as a whole. In this thesis, the design of a seamless hybrid wired and wireless interconnection network for multichip systems in a package is proposed. The design utilizes on-chip wireless transceivers with dimensions spanning up to tens of centimeters. It manages to seamlessly bind both intrachip and interchip communication architectures and enables direct chip-to-chip communication between the internal cores. It is shown through cycle accurate simulations that the proposed design increases the bandwidth and reduces the energy consumption when compared to the state-of-the-art wireline I/O based multichip communications